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Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

Abstract: FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22nm node 6T-SRAM cell. Key in this work was achieving the required CD and profile target specs for the fin and the gate level. Also, the implant levels, though still a 450nm pitch, turned out to be more difficult than expected because of the underlying topography. All this work resulted in the first electrically functional 22nm node SRAM cell, with the contact and metal level exposed on the ASML EUV α-demo tool. [Copyright &y& Elsevier]