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This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs. [ABSTRACT FROM AUTHOR]

When processing Si nanowire based Tunnel Field Effect Transistors (TFETS's), a significant reduction of B diffusion with decreasing nanowire diameter is observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In this study, Ultra High Voltage Electron Microscopy (UHVEM) is used to study in situ the formation of self-interstitial clusters in nanowire based TFET containing samples prepared by Focused Ion Beam (FIB) thinning. Si nanowires with diameters ranging from 40 to 500 nm are irradiated in an UHVEM using different fluxes of 2 MeV electrons at temperatures between room temperature and 375 °C. A strong dependence of defect formation on nanowire radius and on dopant concentration and type is observed. The UHVEM observations are compared with simulations based on quasi-chemical reaction rate theory and with two dimensional dopant concentration distributions determined with high-vacuum Scanning Spreading Resistance Microscopy (SSRM). (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Si nanowire-based Tunnel-Field Effect Transistor (TFET) characteristics are intensively studied as function of nanowire diameter and doping. A significant reduction of B diffusion with decreasing nanowire diameter is e.g. observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In an Ultra High Voltage Electron Microscope (UHVEM), the formation of self-interstitial clusters can be studied in situ while varying e-beam flux, irradiation temperature, impurity concentration and capping layers surrounding the nanowires. Results are presented on {113}-defect formation in Si nanowires with diameters between 40 and 500 nm. The Si nanowires are embedded in SiO2 and are etched into an epitaxial Si stack on a heavily As doped Si substrate. The top layer of the epitaxial stack is in situ B doped or B implanted. In situ UHVEM studies are performed on focused ion beam prepared cross-section samples, irradiating with different fluxes of 2 MeV electrons between room temperature and 375 °C. A strong dependence of {113}-defect formation on nanowire radius and doping is observed. The observations are compared with simulations based on quasi-chemical reaction rate theory. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation (100)/(110)) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current. [ABSTRACT FROM AUTHOR]

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (Wfin = 10 nm) and tall (Hfin = 60-80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain. induced barrier leakage characteristics of 45 mV/V at Vdd = 1 V and Lg = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the VT at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (Wfln = 65 nm) with Idsat = 380 µA/µm at Ioff = 60 nA/µm and Vdd = -1.2V. [ABSTRACT FROM AUTHOR]

Abstract: We report on the process integration of vertical silicon Tunnel FETs (TFETs) and analyze the impact of process and geometrical parameters on the device behavior. The gate–source overlap is shown to be a critical parameter, especially when the overlap is marginal. The temperature dependence also suggests that trap-assisted tunneling injection mechanism is at the origin of the degraded onset characteristic of the vertical TFET, likely due to a large interface trap density and that improvement in the passivation of the surface of the vertical nanowires should be beneficial. [Copyright &y& Elsevier]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

Abstract: We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46μA/μm at V DD of −1.2V and I OFF of 5pA/μm for Si pTFETs is reported. The enhanced current is given by the position of the silicide at the n+side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices. [Copyright &y& Elsevier]

Abstract: High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO2-TiN gate stack shows more than 20% improvement in the drive current at a constant I OFF for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs. [Copyright &y& Elsevier]

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14. [ABSTRACT FROM AUTHOR]

In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS. [ABSTRACT FROM AUTHOR]

Abstract: Electron beam induced current (EBIC) measurements can be used to visualize depletion region in semiconductor junction structures. In this work we use a nanoprober setup to create local contacts to nanowire (NW) based tunnel-field-effect-transistors (TFET), which are gated p–i–n diodes, and perform EBIC measurements to investigate dopant diffusion effects in the junction region of TFET structures fabricated with high and low thermal budget. For contacting we use commercial tungsten probes and in-house fabricated conductive diamond tips. The results show that nanoprober based EBIC measurements are a straight forward way to study the functionality of a large number of NWs simultaneously while also allowing to make an in-depth investigation of the junction position as a result of different processing conditions of the nanowire transistors. [Copyright &y& Elsevier]

Abstract: In this work, we extend the modified shift and ratio method, originally used for extracting the effective channel length in standard short channel MOSFETs, to the extraction of the fin width in FINFET devices. Using devices with different fin widths, the electrical width of the devices can be extracted. The method is adapted in such a way that it takes into account the difference in mobility due to the different crystal orientation of the fin sidewalls and top surface, the width dependence of the threshold voltage and the influence of the increasing source/drain resistance for narrow fin devices. [Copyright &y& Elsevier]