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In this work, performance of Double Gate Gaussian Doped Negative Capacitance Junctionless Transistor (DGGDNCJLT) has been studied for temperature range 200–500 K to explore the suitability of the d...

In this paper, we study the impact of vertical Gaussian doping (GD) profile and ferroelectric (FE) negative capacitance phenomenon on the performance of nanoscale double-gate junctionless (JL) transistor. The device characteristics have been obtained by using the baseline approach of combining Landau–Khalatnikov equation with TCAD simulations. Doped HfO2 has been incorporated as FE gate insulator and parameters such as coercive field ( ${E}_{c}$ ) and remanent polarization ( ${P}_{r}$ ) have been optimized to achieve nonhysteretic voltage amplification along with substantial gain. The impact of GD profile in the channel and FE gate insulator is examined by studying device characteristics for a wide range of projected range ( ${R}_{p}$ ), straggle ( $\sigma$ ), and peak doping ( ${N}_{\mathbf {pk}}$ ) values for optimized ${E}_{c}$ and ${P}_{r}$ . It has been demonstrated that the proposed device exhibits reduced leakage current, increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by 4 orders, and approximately 2 times improvement in ${g}_{m}/{I}_{d}$ values compared to the conventional double-gate GD JL transistor. Furthermore, the proposed device exhibits reverse drain induced barrier lowering effect which leads to increase in barrier even in nanoscale regime.

In this work, the negative capacitance phenomenon exhibited by ferroelectric materials has been incorporated in Junctionless Cylindrical Surrounding Gate (JLCSG) transistor and an analytical model has been developed to study the electrical characteristics of the device by taking into account Landau Khalatnikov equation along with parabolic potential approximation. Using the derived model various electrical parameters such as potential, gain, drain current, gate capacitance etc have been obtained. Silicon doped hafnium oxide has been incorporated as the ferroelectric material and exhaustive study has been done to study the impact of interfacial layer and metal workfunction on device characteristics as these have significant impact on the performance of Junctionless devices. It has been demonstrated by analytical model and TCAD simulations that by incorporating ferroelectric layer and optimizing metal work function and interfacial layer thickness, the device performance of JLCSG can be substantially improved.

In this work, we present a study that explores the suitability of Double Gate Ferroelectric Junctionless Transistor (DGFJL) incorporating Si:HfO2 for high temperature applications. At present, very few studies are focussed on Si:HfO2 to investigate its integrability in the present CMOS design space. Therefore, in the present study, using analytical modeling and TCAD simulations, it is demonstrated that Si:HfO2 based DGFJL exhibits superior performance in terms of substantial gain, reduced leakage currents, improved current drivability and high Ion/Ioff ratio at elevated temperatures as compared to the DGJL counterpart. The study, thus, highlights the fact that DGFJL is a potential candidate for device applications at high temperatures.

In this work the performance of Junctionless Gaussian Doped Negative Capacitance Silicon-on-Insulator (JLGDNCSOI) transistor has been explored to examine the suitability of device for various analog and digital applications. The Negative Capacitance phenomenon of ferroelectric layer along with vertical Gaussian doped channel significantly enhances the performance of JL devices. To explore the electrical characteristics of JLGDNCSOI transistor TCAD models along with Landau-Khalatnikov equation which takes into account properties of Hafnium oxide based ferroelectric layer such as coercive field and remanent polarization have been used. It has been demonstrated that device exhibits substantially improved transfer characteristics, output characteristics, transconductance generation factor, output conductance and unity gain frequency.

In this work we have proposed an analytical model for Double Gate Ferroelectric Junctionless Transistor (DGFJL), a novel device, which incorporates the advantages of both Junctionless (JL) transistor and Negative Capacitance phenomenon. A complete drain current model has been developed by using Landau-Khalatnikov equation and parabolic potential approximation to analyze device behavior in different operating regions. It has been demonstrated that DGFJL transistor acts as a step-up voltage transformer and exhibits subthreshold slope values less than 60 mV/dec. In order to assess the advantages offered by the proposed device, extensive comparative study has been done with equivalent Double Gate Junctionless Transistor (DGJL) transistor with gate insulator thickness same as ferroelectric gate stack thickness of DGFJL transistor. It is shown that incorporation of ferroelectric layer can overcome the variability issues observed in JL transistors. The device has been studied over a wide range of parameters and bias conditions to comprehensively investigate the device design guidelines to obtain a better insight into the application of DGFJL as a potential candidate for future technology nodes. The analytical results so derived from the model have been verified with simulated results obtained using ATLAS TCAD simulator and a good agreement has been found.

The present analysis is focused on studying the effect of ferroelectric (FE) insulator layer and non-uniform doping on the performance of short channel planar SOI Junctionless transistor. The channel is considered to be non-uniformly doped in vertical direction and hafnium oxide based ferroelectric material is considered in the gate stack. The device behavior has been studied by obtaining various device characteristics and the effect of FE insulator layer thickness along with doping profile parameters such as straggle and projected range has been explored. It has been observed that incorporation of non-uniform doping and ferroelectric layer significantly improves the performance of planar SOI Junctionless transistor.

In the present work, the impact of high-k spacers and Negative Capacitance (NC) has been examined on the performance of nanoscale Double Gate Junctionless Transistors by self consistently solving Landau Khalatnikov equation with TCAD simulations. Ferroelectric hafnium oxide is considered in gate stack with interfacial layer of silicon dioxide. The impact of different dielectric constants of spacer and different spacer lengths have been explored extensively on various electrical parameters. It has been demonstrated that high-k spacers significantly improve the gate controllability, thereby, further enhancing the negative capacitance (NC) effect of ferroelectric layer on device operation. The subthreshold swing values as low as 10mV/dec have been obtained along with substantial improvement in I on /I off ratio (about 3 orders), thereby, indicating suitability of the device for future ultra low power electronic applications.

In the present work, performance of short channel symmetric Double Gate Gaussian Doped Ferroelectric FET (DGGDFEFET) has been studied by using fully coupled TCAD simulations with Landau Khalatnikov equation. Ferroelectric layer of PVDF-TrFE (polyvinyledenedifluoride-trifluoroethylene) is considered as gate insulator with an intermediate layer of SiO 2 . The channel is non-uniformily doped in vertical direction and the analog and digital performance of DGGDFEFET has been investigated by obtaining transfer characteristics, subthreshold swing, transconductance ($g_{m}$), transconductance generation factor (TGF), output characteristics and output conductance ($g_{d}$). It has been demonstrated that due to negative capacitance and vertical non-uniform doping, DGGDFEFET shows superior analog and digital performance since it offers super steep transfer characteristics and substantially improved TGF and output characteristics.

In the present work, the impact of Negative Capacitance (NC) effect of ferroelectric materials has been studied on Elliptical Gate All Around Junctionless Transistors by incorporating these materials as gate insulator. Landau Devonshire theory and parabolic potential approximation has been used to develop an analytical model to obtain various electrical parameters like surface potential, gate capacitance, subthreshold slope etc. The effect of varying aspect ratio (AR) has been incorporated in the model by obtaining effective radius depending on lengths of major and minor axes. Using the developed model a comparative analysis has been done for devices with two different ferroelectric materials, PZT and SBT, to investigate the feasibility of these materials for integration into future CMOS technology. It has been observed that for different aspect ratios, the device exhibits gain > 1 which also leads to point subthreshold swing value as low as 9mV/dec for SBT and 11mV/dec for PZT for a small range of applied bias, thereby, signifying suitability of such devices for sub-60mV/dec, low power applications.

In this work, we have theoretically investigated the impact of temperature dependent Negative Capacitance (NC) effect on electrical characteristics of long channel Double Gate Ferroelectric Junctionless Transistor for temperature range 280 to 340K. We have considered metal-ferroelectric-semiconductor (MFS) structure and incorporated ferroelectric material Strontium Bismuth Tantalate (SBT) as gate insulator. The impact of temperature variation on electrical parameters such as surface potential, gain, gate capacitance, and mobile charge density has been studied. It has been observed that internal voltage amplification decreases with increase in temperature. Also, degradation of gain and gate capacitance is observed with gradual increase in temperature.

In this work high temperature performance of Elliptical Gate Ferroelectric Junctionless Transistor has been theoretically investigated and a temperature dependent analytical model has been developed to examine the effect of elliptical cross section along with negative capacitance (NC) phenomenon on junctionless devices. The electrical characteristics of Elliptical Gate Ferroelectric Junctionless Transistor have been studied for temperature range 300K to 360K and Strontium Bismuth Tantalate (SBT), a ferroelectric material has been considered as the gate insulator. The impact of temperature variation along with change in aspect ratio has been examined on various electrical parameters such as surface potential, gain, gate capacitance and subthreshold slope. It has been observed that voltage upconversion achieved due to NC phenomenon exhibited by ferroelectric material is less for device with aspect ratio 1, thereby, signifying its suitability for high temperature energy efficient applications.

We have developed a complete drain current model to study the impact of negative capacitance phenomenon exhibited by ferroelectric materials in Symmetric Double Gate Junctionless Transistor using Pao-Sah current formulation and Landau Devonshire theory. Strontium Bismuth Tantalate (SBT) is used as gate insulator and no interface layer is considered in the analysis i.e. metal-ferroelectric-semiconductor (MFS) structure has been studied. Using the analytical model the various parameters obtained are gain, gate capacitance, subthreshold swing, threshold voltage, mobile charge density and drain current. It has been observed that values of gain>1 and subthreshold swing

In this paper we have developed an analytical model for Double Gate Ferroelectric Junctionless (DGFJL) transistor using Landau's theory and parabolic potential approximation. We have obtained expressions for surface potential and electric field and have demonstrated negative capacitance effect provided by ferroelectric layer. The results also demonstrate the step-up conversion capability of this device, thereby signifying improved gate control and the suitability of this device for low voltage/low power switching applications.