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Abstract: This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance. [Copyright &y& Elsevier]

We report on the study of the electrical and material properties of n-Ge contacts with a thin Si-passivation layer. n-Ge contacts typically show Fermi-level pinning and low dopant activation which results in too large specific contact resistivities of >10-4 Ω cm2 and which impedes applications such as high performance Ge complementary metal-oxide semiconductor technology. In this work a thin in situ doped (1×1020 cm-3 of phosphorus) epitaxial Si-passivation layer is grown selectively on n-Ge, followed by a Ti/TiN stack deposition. The insertion of this thin Si-passivation layer reduces the pinning and activation limitation, achieving specific contact resistivity values of ∼1×10-6 Ω cm2. Physical modeling of the specific contact resistivities was performed, providing the insight validating the underlying explanation of the improvement. Key factors for the contact resistivity lowering are the good alignment of the Si and Ge conduction bands and the higher doping concentration achieved in Si. [ABSTRACT FROM AUTHOR]

Abstract: We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46μA/μm at V DD of −1.2V and I OFF of 5pA/μm for Si pTFETs is reported. The enhanced current is given by the position of the silicide at the n+side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices. [Copyright &y& Elsevier]

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14. [ABSTRACT FROM AUTHOR]

Abstract: At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 ]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (W fin) and gate length (L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10nm. [Copyright &y& Elsevier]