1. Narrowing the margins with elastic clocks
- Author
-
Juan A. Moya, Jonas Casanova, Jordi Cortadella, Djavad Amiri, F. Martorell, Luca Necchi, Emre Tuncer, Luciano Lavagno, Danil Sokolov, Carlos Macian, Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, and Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
- Subjects
Engineering ,Circuits integrats -- Disseny i construcció ,business.industry ,Process (computing) ,Differential (mechanical device) ,Enginyeria electrònica::Microelectrònica::Circuits integrats [Àrees temàtiques de la UPC] ,Noise (electronics) ,Synchronization ,Die (integrated circuit) ,Reduction (complexity) ,Delay circuits ,Control theory ,Robustness (computer science) ,Electronic engineering ,Integrated circuit manufacture ,business ,Integrated circuits -- Design and construction ,Voltage ,Clocks - Abstract
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.
- Published
- 2010