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This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13- $\mu \text{m}$ standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain–source current nonlinearity. This also reduces distortions due to drain–source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM–AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a −35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

A dual-mode radio frequency CMOS power amplifier (PA) for Internet of Things application is presented, which is integrated with the other circuits in a 55-nm bulk CMOS process. The low-power mode is achieved by reducing the number of turn-on power transistors, which are also used for linearization. The PA has a gain control scheme that functions by controlling the transconductance ( ${g_{m}}$ ) of the driver stage. A simple body network is introduced to common gate power transistors to improve the linearity of the PA. It is measured with 802.11n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 16 dBm with a supply current of 222 mA under an error-vector-magnitude of −27 dB, which is packaged in a QFN 5 ${\times } \,\, 5$ mm.

This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling technique is proposed. It is able to cancel all the leakages caused by antenna reflection, asymmetry of a balanced structure, and lossy substrate without additional power or area. Even-order harmonic leakages from the power amplifier (PA) are also reduced by an even-harmonic filter, which is implemented simply by removing the real ground from the symmetrical point of the PA output transformer. Matching networks are simplified by using a modified coupler structure. A low-noise combining amplifier is used to make the combining circuit compact. As a result, the transceiver achieves the output power of −1.6 dBm, the phase noise of −105.44 dBc/Hz at 1MHz offset, the receiver (Rx) gain of 15.3 dB, and the noise figure of 11.6 dB. Tx leakages are canceled so that the isolation between Tx and Rx is 47.3 dB. The chip consumes 74.1 mA from a 1.5-V power supply. Despite the high integration level, the chip area including pads is 1.7 mm $\times $ 0.9 mm. A $ {K}$ -band FMCW radar module with a single antenna is implemented with this chip.

A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- $\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm $P_{\mathrm{OUT}}$ , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm $P_{\mathrm{OUT}}$ , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

A CMOS common-gate (CG) combining power amplifier is introduced, which has a simple load impedance adaptor. The CG stage of a cascode amplifier consists of a main amplifier with a load impedance adapter and an auxiliary amplifier with a phase compensator, which are biased for classes AB and C, respectively. The proposed configuration not only increases the efficiency of the power amplifier (PA) at back-off powers, but also increases the linearity at high output powers by canceling AM–AM and AM–PM nonlinearities of the main amplifier with those of the auxiliary amplifier. A load impedance adaptor can be used to match two different optimum load impedances of the main and auxiliary amplifiers simultaneously. A phase compensator is introduced to match the output phases of both amplifiers. It has a die size of $0.9 \times 1.63$ mm2 operates at 2.484 GHz with a 3.3 V supply, which is implemented with the 0.18- $\mu \text{m}$ CMOS technology. It shows a linear output power of 22.1 dBm with a PAE of 32% for an 802.11 n signal at error vector magnitude (EVMs) of −25 dB, and it also shows apparent efficiency improvements at back-off powers.

This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode–cascade configuration. The proposed configuration improves AM–PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier. In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off. The PA is implemented in 0.18- $\mu \text{m}$ CMOS process with an output combining network in printed circuit board. It provides an average power of 24.5 dBm with a PAE of 45.6% for a long-term-evolution 10-MHz up-link signal with the ACLRE–UTRA of −30 dBc at 2 GHz.

Austenitic stainless steels and associated welds have been widely used for the pressurizer surgeline of the pressurized water reactors (PWRs). Though the amount of the ferrites in the welds is generally low, the relatively high operating temperature of surgeline may cause the degradation of fracture resistance due to thermal aging during the long-term operation. In this study, the mechanical property changes caused by the thermal aging were evaluated for the ER316L and ER347 welds as well as CF8 M. The materials were thermally aged at 400 C for 5,000 h and the properties were measured at room temperature and 320 C. The fracture resistance was measured using 1/2T-CT specimen by normalization method. In addition, small punch (SP) test was performed at both temperatures and the results were used to estimate the tensile property and fracture resistance of the stainless steel welds and CF8 M. Based on the results, correlations were developed to estimate the fracture resistance using the load-displacement curve of SP tests. Also, the fracture surfaces of CT and SP test specimens were compared and discussed in view of the effect of thermal aging on microstructure.

A reconfigurable adaptive power cell configuration for a multi-band CMOS power amplifier (PA) is presented, for long-range WLAN applications. The common gate (CG) transistor of a CMOS cascode power cell consists of four differently biased 4-transistor cells to have good linearity, two of which are subsidiary cells and are turned off to cover the higher frequency band. This allows the PA to operate in multi-band properly without any additional switches or paths for multi-band. The chip is fabricated in 40 nm CMOS technology, and its size including the ESD-protected pad is $1.985\times 1.61\ \text{mm}^{2}$ . The measurement results show that the proposed PA achieves the output power of 27.8 (28.2) dBm with the PAE of 52% (53%) at a high (low) frequency band.

A 2-stage 1.7-GHz Doherty power amplifier (PA) with an adaptive bias (ADB) circuit was designed for small-cell base station applications. An uneven power cell size ratio was used to provide a large back-off efficiency for high peak-to-average power ratio (PAPR) signals. To simplify the power divider and inter-stage matching network, a lumped Lange-type quadrature coupler was used. The leakage signal from the isolated port of the coupler was used as an input signal for the ADB circuit of the peaking amplifier. The PA was implemented in a 0.25-μm GaN on a SiC MMIC process. For a 1.7-GHz continuous wave, the PA has a 45.8% power added efficiency (PAE) at the output power of 38.6-dBm and a 31.2% PAE at 7-dB back-off power. For an LTE downlink signal, adjacent channel leakage ratio (ACLR) of −25.9-dBc was obtained at the average output power of 31.4-dBm without a digital pre-distortion (DPD).

This paper reports a unique 4-terminal MEMS relay (actuation is electrically isolated with signal passage) employing a novel one-contact design to overcome high contact resistance problem of the conventional 4-terminal MEMS relay which utilizes a typical two-contact design. The fabricated 4-terminal MEMS relay with the one-contact design demonstrated a contact resistance of 18 mΩ, which is two order-of-magnitude lower value than that of the conventional two-contact design. To the best of our knowledge, this result is the lowest value in the 4-terminal MEMS relay and comparable value with the state-of-the-art in 3-terminal MEMS relay [14]. In addition, the relay was operated up to 1.1 × 106 cycles at 1 V / 50 mA in an air and hot switching condition with negligible contact resistance variation. The lifetime is 10 times longer than that of the conventional 4-terminal MEMS relay.

In this letter, we propose and demonstrate a digitized intermediate frequency (IF)-over-fiber transmission system based on the delta-sigma modulation technique as a means of digitizing an analog IF signal. Using a realized 130-nm CMOS, two-level third-order low-pass delta-sigma modulator (DSM) chip operating at 622.08 MHz, a 64-Quadrature Amplitude Modulation long-term evolution (LTE) 10-MHz signal at a 10-MHz IF frequency was successfully digitized, transported over an emulated digital fiber-optic link, and analyzed in terms of signal spectra, error vector magnitude (EVM), and constellations. The difference between power levels of the received LTE IF signal and quantization noise due to the developed DSM was larger than 45 dB, and an EVM value of 2.48% for the received LTE signal was obtained.

The miniaturized radar sensor for detecting short distances is realized using a six-port network. The six-port network of the radar sensor consists of passive components and RF power detectors. The power detector obtains a highly accurate DC voltage because DC offsets are cancelled using a dummy structure in the detector. The maximum error of a distance measurement to 3 m is approximately 2% for a single target. Using traveling wave antennas, the distances to two targets with different directions are measured with 6.7% maximum detection error to 1 m. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2634–2637, 2014

This brief presents a fully integrated CMOS receiver that is capable of dual-mode frequency-modulated continuous-wave (FMCW) and ultrawideband (UWB) radar operations using the 0.13- $\mu\hbox{m}$ CMOS technology. The circuit consists of a low-noise amplifier, active mixers, an in-phase and quadrature generator, and buffers. In the proposed receiver, not only the gain but also the bandwidth of the overall receiver can be tailored by the switching of the center frequencies of stages and without lowering the quality factor of each stage. As a result, the receiver achieves a conversion gain of 36.7 dB, a 1-dB power gain compression point (P1dB) of $-$ 29.7 dBm, and a double sideband (DSB) noise figure (NF) of 6.1 dB in the narrowband FMCW mode. The receiver also achieves a conversion gain of 27.4 dB with a 3-dB bandwidth of 6.1 GHz, a P1dB of $-$ 21.6 dBm, and a DSB NF of 7.4 dB in the UWB pulse mode. Its performance is comparable with that of previously published chips that only operate in a single mode.

This paper presents a wireless power transfer (WPT) system for powering implantable biomedical devices; the system is configured to achieve high efficiency even with CMOS switches and printed-circuit-board pattern coils and to maintain constant output voltage against coupling and loading variations without any additional blocks. It is shown that the parallel-resonant transmitter (TX) and receiver (RX) topology is advantageous for high efficiency even with lossy but compact components. In addition, the output voltage of the topology is insensitive to coupling and/or loading variations if the operating frequency is automatically adjusted according to coupling variations. A parallel-resonant class-D oscillator TX is developed to track the optimum operating frequency for the constant output voltage. The operating distance for the constant output voltage is also extended using a novel resonator structure, which contains two resonating coils. These proposed schemes allow a compact, efficient, and robust wireless power system. Maximum power of 174 mW can be transmitted with 63% overall efficiency.

We present a synchronization method and coherent ultra-wideband transceivers for a widely separated multiple-input multiple-output (MIMO) radar. Synchronization is essential for MIMO operation, but a spatially spread radar array is not a good structure for it. A wireless cooperative synchronization method is based on coherency of pulse signals and highly accurate delay estimation and they are implemented through a coherent pulse generator and a fine delay-based receiver. Distance measurements of a radar transceiver (TRX) show that the maximum mean error is 4 mm for the target in a range of 0.2 m-8.0 m. Synchronization measurements of two radar TRXs show that the maximum mean error of the asynchronous time difference is 11 ps for the target in a range of 0.25-8.0 m. 2-D images for multiple targets and fluctuational radar cross sections are achieved with the proposed synchronization method under MIMO operation.

This letter presents a dual-mode multi-band second harmonic controlled SOI LDMOS power amplifier (PA). A mode selection switch is designed to have better power handing capability than a conventional switch, which improves performance in low power mode (LPM). To improve the PA's linearity in high power mode (HPM), second harmonic is controlled with the aid of a path for LPM. The PA, implemented with a 0.13- $\mu$ m SOI LDMOS process, operates in triple bands (band 5, 8, and 20) with dual power modes. It is measured using a 16 QAM long-term evolution (LTE) signal with a 10 MHz bandwidth. At 850 MHz, the results show 27.7 dBm average output power (Pout), 31.4 dB gain, and 31.4% power-added efficiency (PAE) with 4% error-vector magnitude (EVM) in HPM and 10.4 dB gain, 15.5 dBm Pout, and 22.5% PAE with 4% EVM in LPM with the LTE signal.

This paper presents a 77-GHz CMOS power amplifier (PA) with a parallel power combiner based on a transmission-line transformer (TLT). An inter-stage matched cascode power cell structure is applied to obtain high output power and efficiency, where a simple matching network between the common-gate and common-source stage is introduced. The parallel power combiner based on a broadside-coupled TLT is analyzed and compared with a series power combiner. The PA is fabricated using a 65-nm RF CMOS process. It achieves the saturated output power of 15.8 dBm, the power-added efficiency of 15.2%, and the power gain of 20.9 dB with a supply voltage of 2.0 V at 77 GHz.

A dual-power-mode output matching network for a digitally modulated power amplifier (DMPA) to improve low power efficiency is proposed. The DMPA with output matching network is fully integrated using a 0.13- $\mu$ m RF CMOS process. The matching network incorporates a switched transformer and capacitors. The switched transformer is proposed for tuning its inductance to have two power modes. It is designed to minimize losses due to parasitic components of the switch transistor. The DMPA has a 12-bit resolution to enable a wide digital transmit power control (TPC) range. The peak power is 29.3 dBm with 34% efficiency. The efficiency at 16 dBm is improved from 8% to 13% by using the output matching network. Simple static predistortion helps the DMPA reconstruct 27.9-dBm WCDMA signals at 1.95 GHz with 31% efficiency. The digital TPC range is 25 dB.

A low-noise ultrawideband CMOS mixer circuit for the down conversion of a K-band signal is presented. A bleeding path gm-boosting technique is proposed, which reduces the effect of noise sources of the proposed mixer. The measurement results show that the minimum noise figure is 3.61 dB at 24 GHz when consuming 2.6 mW at a 1.5-V supply voltage. The results also show a conversion gain of 9.15 dB, a of P1dB of -13 dBm, and an isolation of a local oscillator port to a radio frequency port of -40 dB. The circuit was fabricated using 0.13-μm CMOS technology with a chip area of 0.68 x 1.07 mm2.

This paper demonstrates the implementation of a hybrid polar linear amplification with nonlinear components (LINC) power amplifier (PA) that uses the combination of polar and LINC schemes. The hybrid polar-LINC operation is based on the idea of representing envelope information with the combination of the two schemes. The high bandwidth burden of a supply modulator in a polar transmitter can be effectively relieved, and the back-off efficiency of a LINC transmitter is improved. The implementation is accomplished with a CMOS PA and a CMOS supply modulator. The designed PA includes a class-E amplifier and the proposed output combiner, which is based on a transmission line transformer with isolation resistors. Since the combiner keeps the operating condition of PAs intact regardless of the phase differences, out-phased signals for LINC can be linearly combined. The implemented hybrid polar-LINC architecture, including the PA and a supply modulator, has a 28.5-dBm maximum linear power and 29.6% efficiency without any pre-distortions.

A CMOS linear power amplifier for wireless local area network IEEE 802.11b/g application is presented. To achieve high linear output power and high efficiency, a large-signal multigated transistor linearization method is proposed with an envelope injection gate bias circuit. A novel inter-stage matching transformer, which functions as a power splitter, is designed to implement this method. It is fabricated with a TSMC 0.13-μm standard RF CMOS process. Measurement shows 19.5-dBm Pout with 24.8% power-added efficiency (PAE) at - 25-dB error vector magnitude with an orthogonal frequency-division multiplexing 64-QAM 54-Mb/s 802.11g signal source and 23.15-dBm Pout with 31.73% PAE with DSSS, CCK, and 11-Mb/s 802.11b signal source without digital pre-distortion.

It is shown that the distance of wireless power transfer is significantly increased by placing intermediate resonators (repeaters) between transmitter and receiver. The guidelines are provided to use the repeaters effectively. We first briefly review how the repeaters enhance the transfer distance. Next, the aspect of resonant frequency splitting is studied separately both for even and odd numbers of repeaters. The transferred power, efficiency, and output impedance phase are evaluated for each repeater configuration. These provide the guidelines to select the optimum repeater positions and numbers. We also propose and study a new kind of repeater which can be placed (biased) even in the vicinity of transmitter or receiver. This increases the flexibility in choosing the repeater position. The net effect of such biased repeater is approximately doubling the effective coupling coefficient between transmitter and receiver. Experimental results are provided to prove the concepts.

In this paper, a 24 GHz phase-tunable resistively-coupled VCO is presented. The proposed VCO consists of two identical VCOs which are coupled through resistors. By differentiating free-running frequencies of two VCOs by controlling variable capacitances of their respective resonators, continuous phase difference between the VCOs upto 90° could be established. This shows the phase noise of −95.3 dBc/Hz and tuning range of 11.8 % with 18 mW DC power consumption. This is fabricated using 0.13 um CMOS process with its chip area of 1×1 mm2. The phase difference tuning capability of coupled oscillators can be used in some applications.

This paper presents a compact K-band Doppler radar sensor for human vital signal detection that uses a radar configuration with only single coupler. The proposed radar front-end configuration can reduce the chip size and the additional RF power loss. The radar front-end IC is composed of a Lange coupler, VCO, and single balanced mixer. The oscillation frequency of the VCO is from 27.3 to 27.8 GHz. The phase noise of the VCO is ?91.2 dBc/Hz at a 1 MHz offset frequency, and the output power is ?4.8 dBm. The conversion gain of the mixer is about 11 dB. The chip size is 0.89×1.47 ㎟. The compact Ka-band Doppler radar system was developed in order to demonstrate remote human vital signal detection. The radar system consists of a Ka-band Doppler radar module with a 2×2 patch array antenna, baseband signal conditioning block, DAQ system, and signal processing program. The front-end module size is 2.5×2.5 ㎠. The proposed radar sensor can properly capture a human heartbeat and respiration rate at the distance of 50 cm.

A CMOS power amplifier (PA) with a built-in RF predistorter is proposed to improve the predistortion system efficiency, especially for handset applications. To eliminate the power consumption of an external predistorter and digital-to-analog converters in the control signal paths, the driver stage of the proposed PA has gain and phase control abilities according to two digital control words. This compensates for the distortions of the PA with envelope-dependent gain and phase control. It is implemented in a 0.18-μm RF CMOS process. The measurement results show 8.7 dB of gain control range and 49.4° of phase control range, which can compensate for the distortions of the designed PA. Using a WCDMA modulated signal, the PA improves its linear output power from 27.2 to 29.1 dBm and its linear efficiency from 34.8% to 41.1% by RF predistortion.

This paper presents a K-band CMOS UWB radar transmitter with highly accurate variable delay circuits and a bi-phase modulating pulsed oscillator. The UWB radar transmitter is composed of three blocks: variable delay circuits that consist of a digital synchronized counter and a Vernier delay line (VDL), a baseband control signal generator, and a pulsed oscillator. The VDL allows a high range accuracy level of several millimeters. Asymmetric signals generated by the baseband control signal generator can control the phase of each output pulse. Because the pulsed oscillator operates only for the duration of a pulse, it has an extremely low level of DC power consumption and no LO leakage. It is fabricated with 0.13-μm CMOS technology and a chip with dimensions of 0.98 mm × 0.69 mm. The output spectrum is centered at 26.0 GHz, and the pulse width is controllable from 280 to 680 ps. The peak output power is about 2 dBm.

A fully integrated 24-GHz CMOS ultra-wideband (UWB) radar transmitter for short-range automotive application is presented. For high-range resolution and improved signal-to-noise ratio, a pulse compression technique using binary phase code is adopted. Design issues of UWB radar transmitter are investigated based on fundamental pulse theory. A pulse former, which operates as a switch to generate a pulse modulated carrier signal and a bi-phase modulator for pulse compression, is proposed. The proposed transmitter achieves 4-GHz output signal bandwidth, which means a minimum range resolution of 7.5 cm, and the total dc power dissipation is 63 mW.

A CMOS power amplifier (PA) with a compact spiral-shaped directional coupler for a mobile UHF RF identification (RFID) reader is proposed here, and its output power combiner and the directional coupler are implemented using an integrated passive device process. The two-chip solution not only enables a CMOS PA to be highly efficient, but also allows the directional coupler and the power combiner to be mounted in a compact standard package. A polar transmitter is implemented using the CMOS PA with the directional coupler to verify the operation of the proposed configuration for a UHF RFID reader. Measurements indicate that the CMOS PA with the directional coupler transmits 27.3 dBm of output with 44.6% of power-added efficiency and that the implemented polar transmitter satisfies the required UHF RFID reader specifications.

This paper presents a wideband transformer-coupled CMOS power amplifier (PA). On-chip transmission-line transformers are used as key components of matching networks at output, input, and interstage. The wideband on-chip transformer is harnessed without any additional inductive devices so that a wideband power characteristic can be achieved. The PA is fabricated using a 0.18-μm CMOS process. It provides a saturated output power of 21.5 dBm with the power-added efficiency (PAE) of 20.3%, and the output 1-dB gain-compressed power (P1 dB) is 20.2 dBm with the PAE of 14.8% at 9.5 GHz, respectively. The small-signal gain is 25.3 dB and the 3-dB bandwidth is 6.5 GHz (6.5-13 GHz). The die area is 1.34 mm × 0.47 mm. Among the reported X/Ku-band CMOS PAs, this amplifier achieves the highest figure of merit, and also shows suitable performances for phased-array systems.

A Doherty Power Amplifier (PA) with the proposed GaN MMIC for femtocell base stations is presented. The MMIC was fabricated using a 0.25 μm TriQuint GaN process. An on-chip quadrature coupler based on a lumped magnetic coupler with capacitors was used to reduce the chip size. The MMIC with an area of 2.5 × 2.7 mm2 includes an input matching circuit, a driver transistor, carrier and peak transistors at power stage, and an inter-stage matching network with the quadrature coupler. The Doherty PA with MMIC shows 56.2% power added efficiency (PAE) with a gain of 19.7 dB when the output power is 41.2 dBm for a 2.14 GHz CW signal. For a down link WCDMA signal, the PAE of 39.6% is achieved at an output power of 35.3 dBm. The Doherty PA with the MMIC presented here has a small effective module area of 7 × 15 mm2, which can be readily reduced further.

A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.

A fully integrated 0.13-μm CMOS receiver for ultra-wideband systems is implemented. This receiver enables eight bands of operation covering 3.1–9.0 GHz. The system, based on the Multiband OFDM Alliance standard proposal and consisting of a direct-conversion receiver chain and required noise figure, is discussed. The average conversion gain and input P1dB are 67.3 dB and −25.4 dBm, respectively. The shunt-series feedback low-noise amplifier provides a receiver front-end noise figure of 7.1–9.5 dB over the entire band. The mixer, based on a folded-cascode topology, also implements a four-stage programmable gain amplifier. A fabricated die has been bonded and molded onto PCB for characterization. The receiver chip dissipates 48 mA from 1.2 V power supply. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:841–845, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25083

Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiers in the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.

In this article, a high-power amplifier for X-band application is studied, which consists of a two-stage amplifier with magnetically coupled power-combiners and dividers. These are based on transmission line transformers, which has lower loss characteristics than spiral-type transformers at the frequencies. The proposed amplifier utilizes the voltage-combining concept with the transformers and differential amplifiers. The size of the amplifier is also minimized by using the virtual grounds of the differential structure. The saturated output power of the power amplifier is 38.1 dBm (6.45 W), and the gain is 17 dB at 10 GHz. The area of the chip is 2.56 mm × 3.13 mm and the power density of the amplifier is 806 mW/mm2. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 110–113, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24851

A class-E power amplifier is proposed in this study. It uses both nMOS and pMOS as switching devices to reduce the voltage stress of each transistor. A voltage-combining scheme with nMOS and pMOS is proposed, and a transformer is designed using this scheme. The power amplifier is implemented in a 0.18-mum RF CMOS process. Measurements show a maximum output power of 30.2 dBm with 36.8% power-added efficiency at a 3.3-V supply voltage. The power amplifier sustains a supply voltage of up to 3.9 V.

A quasi-four-pair structure of an RF CMOS power amplifier (PA) is proposed. The structure is applied to a 1.8-GHz class-E CMOS PA for a global system for mobile communications with a 0.18-mum RF CMOS process. This allows a simple design, as well as a high output power. The transistor size issues of the cascode PA are also studied. An integrated passive device transformer is used as both a power combiner and a matching circuit of the power stage. The results show an output power of 33.4-33.8 dBm and a power-added efficiency of 47.4%-50% with a supply voltage of 3.3 V at a frequency range of 1.71-1.91 GHz.

Various Class-E CMOS power amplifiers for GSM applications are presented. A stage-convertible transformer for a dual mode power amplifier is proposed to increase efficiency in the low-output power region. An integrated passive device(IPD) process is used to reduce combiner losses. A split secondary 1:2 transformer with IPD process is designed to obtain efficient and symmetric power combining. A quasi-four-pair structure of CMOS PA is also proposed to overcome the complexities of power combining.

A differential heterojunction bipolar transistor (HBT) power cell has been designed and modeled with additional model extraction patterns. The differential power cell, which is composed of a unit differential amplifier with a common emitter ballast resistor, has no gain degradation by the ballast resistors and has been implemented in InGaP/GaAs HBT technology. DC and AC characteristics are extracted from a half circuit of the differential power cell and thermal characteristics are extracted from a common-mode circuit of that. Using the extracted model, a 5-GHz differential power amplifier has been designed and fabricated with on-chip output networks. The 5-GHz differential power amplifier delivers 26 dBm of P1dB with 30% collector efficiency. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2262–2268, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23684

This paper describes a transmitter integrated circuit (IC) for 5.8-GHz dedicated short-range communication applications. It consists of a baseband variable-gain amplifier (VGA) and an amplitude-shift-keying (ASK) modulator with an output amplifier. The VGA has exponential gain control characteristics. The proposed temperature- independent exponential gain control is realized with a voltage-to-current converter and n-p-n bipolar transistors. The VGA is powered by 3.3 V with 5 mA. The ASK modulator utilizes the Gilbert topology and consumes 32 mA of current with 3.3-V supply. The conversion gain (in decibels) of the transmitter IC is varied linearly from + 5.3 dB to - 17.7 dB with respect to the control voltage from 0.5 V to 2.5 V. It achieves gain errors of less than plusmn1.2 dB over the 23 dB gain range, an output P1 dB of 3.5 dBm at the maximum gain of 5.3 dB, and an adjacent channel power lower than -45 dBc . It occupies an area of 1770 mum times 1150 mum including the bondpads.

A load-shared CMOS power amplifier (PA) for 1.8-GHz polar transmitter applications has been implemented in standard 0.18-mum CMOS technology and fully characterized to demonstrate its efficiency boosting technique in low power mode. With the aid of cascode amplifiers, the load-shared configuration achieves efficiency improvement at low supply voltage in a polar transmitter. A differential class-E amplifier with a parallel resonant circuit is analyzed and incorporated in the load-shared PA. The load-shared configuration is composed of driver amplifiers (DAs) and PAs whose output loads are shared. The DA has a constant gate voltage biasing of a cascode amplifier for efficiency boosting, whereas the PA has a self-biased cascode configuration to be turned on and off by a supply voltage. The measurement results of the load-shared configuration show a drain efficiency increase from 6% to 30% at 16-dBm output power compared with a conventional self-biased cascode amplifier. The load-shared PA is reported with 35.6% of power-added efficiency and 32.2 dBm of output power at 1.88 GHz.

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2-bit sigma-delta (ΣΔ) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2-bit digitized envelope signals. The 2-bit ΣΔ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over-sampling ratio, this technique is best suited for wireless communication with high data rates.

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.

A 24-GHz single-pole, single-throw (SPST) switch with high isolation is designed using InGaP/GaAs HBT process. To obtain high isolation in an off state, cascode structures are utilized and an ad- ditional shunt transistor is introduced in an output, which helps to reject a leakage signal. Dummy cascode structure is used as a current steering circuit for input matching and short rise/fall time. The fabricated SPST switch shows an effective isolation of 52 dB at 22.8 GHz and 41 dB at 24 GHz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2155-2158, 2008; Published online in Wiley InterScience (www. interscience.wiley.com). DOI 10.1002/mop.23606

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.

This paper presents a novel polar transmitter architecture with a 2-bit sigma-delta modulator. In the proposed architecture, the 2-bit sigma-delta modulator is introduced to suppress quantization noise of conventional sigma-delta modulator. The power amplifier configuration is also modified in a binary form to accommodate the 2-bit digitized envelope signal. The Ptolemy simulation results of the proposed structure show that the spectral property is greatly improved in full transmit band of EDGE system. The fine quantization scheme of the 2-bit modulator lowers the noise level by 10dB without increasing the over-sampling ratio, which may be obtained if the over-sampling ratio increases twofold. Dynamic range is also enhanced up to 5dB owing to the new form of the power amplifier in the transmitter.

This article presents an effective methodology for designing a CMOS single-balanced down conversion mixer with LO cancellation for MB-OFDM UWB direct-conversion receiver. The most crucial drawback of single-balanced mixer; LO feedthrough is overcome by employing BPF technique for multi-channel LO signal. The proposed single-balanced mixer is implemented with 0.18 μm CMOS technology and it operates from 3 to 5 GHz frequency range. The measurement result shows that LO signal amplitude is less than IF signal, the IIP3 is 1 dBm at 4-GHz band, and the current consumption is 6 mA. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2555–2558, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22793

This paper presents a novel 4-bit phase shifter using distributed active switches in 0.18-mum RF CMOS technology. The relative phase shift, which varies from 0deg to 360deg in steps of 22.5deg, is achieved with a 3-bit distributed phase shifter and a 180deg high-pass/low-pass phase shifter. The distributed phase shifter is implemented using distributed active switches that consist of a periodic placement of series inductors and cascode transistors, thereby obtaining linear phase shift versus frequency with a digital control. The design guideline of the distributed phase shifter is presented. The 4-bit phase shifter achieves 3.5 plusmn 0.5 dB of gain, with an rms phase error of 2.6deg at a center frequency of 12.1 GHz. The input and output return losses are less than -15 dB at all conditions. The chip size is 1880 mum times 915 mum including the probing pads.

A CMOS wideband cascaded variable gain amplifier (VGA) with a temperature-independent exponential gain control characteristic is presented in this paper. The exponential gain control function is realized using parasitic bipolar transistors and a control signal converter. The bandwidth is extended using an inductive peaking technique for high-frequency operations. The gain of the VGA varies from -38.8 to 55.3 dB in relation to the control voltage that varies from 0 to 1.8 V. The bandwidth of the proposed VGA is approximately 900 MHz with a gain control range of 94.1 dB. The proposed VGA includes a dc offset cancellation loop to avoid amplification of the dc offset. The VGA is powered by 1.8 V with 11.4 mA. The VGA chip including bondpads occupies an area of 850 mum times 490 mum.

In this paper, we present a receiver front-end and a frequency source suitable for wireless sensor network applications, in which power consumption is severely restricted under several milliwatts. For such an extremely low-power receiver, current-reusing and frequency multiplying schemes are proposed for both the RF front-end and frequency source. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at the 10-MHz intermediate frequency (IF), taking only 500-muA bias current from a 1.0-V supply voltage. The measured phase noise of the fabricated frequency source is -115.83 dBc/Hz at 1 MHz offset from a 2.2-GHz center frequency, taking 840 muA from a 0.7-V supply. The front-end performance is compared with the previously reported low-power front-ends operating in similar frequency ranges