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Inverter-based resources (IBRs) may inject nonconventional or no negative-sequence current during unbalanced faults. The adverse impact of such fault current characteristic has been reported on fault type identification and directional functions that are essential to impedance-based protection. However, the impact of IBR negative current injection on the core part of different implementations of impedance-based protection function has not been thoroughly investigated. Latest German Gird Code introduces a new requirement for IBRs to inject negative sequence current proportional to its measured negative sequence voltage. In this paper, we will investigate if this requirement can address challenges and issues raised by IBRs for protection relays. This paper investigates and compares the impact of IBRs with two options 1- no negative sequence current injection and 2- negative sequence current injection based on latest German code on phase comparator based methods and impedance-based protection functions. Theoretical analysis, software simulation and commercial relay test have been used for this investigation.

A multiplying delay-locked loop (MDLL)-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a phase-locked loop mode to align the coarse phase and an MDLL mode to obtain a delay-lock. With non-overlap dual phase detector pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line from that of delay line. The NTF includes aliasing effect and shows better accuracy than the prior voltage controlled oscillator realignment-based approaches. This clock multiplier occupies an active area of 0.047-mm2 in 40-nm CMOS process. The clock multiplication ratio ( $N$ ) is an integer value from 8 to 27. With a low-cost 19.2-MHz TCXO reference, 153.6–518.4 MHz clocks were successfully generated, and a phase noise of −124 dBc/Hz at 100-kHz offset from a 518.4-MHz clock, rms jitter of 1.28 ps, and −65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 and 1.1 V supplies.

In this paper, we apply various area reduction techniques on an inductor–capacitor ( LC )-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in system-on-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phase-locked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm2 among LC -tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoMjitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons.

Coherent detection offers high spectral efficiency and receiver sensitivity, but digital signal processing (DSP)-based coherent receivers may be prohibitively power hungry for data centers even when optimized for short-reach applications, where fiber propagation impairments are less severe. We propose and evaluate low-power DSP-free homodyne coherent receiver architectures for dual-polarization quadrature phase shift keying (DP-QPSK) for inter- and intradata center links. We propose a novel optical polarization demultiplexing technique, for DP-QPSK and higher-order modulation formats, with three cascaded phase shifters driven by marker tone detection circuitry. We consider carrier recovery based on either optical or electrical phase-locked loops (PLLs). We propose a novel multiplier-free phase detector based on XOR gates, which exhibits less than 0.5 dB power penalty relative to a conventional Costas loop phase detector. We also study the relative performance of homodyne DP-differential QPSK, for which carrier phase recovery is unnecessary. Our proposed DSP-free architectures exhibit ∼1 dB power penalty at small chromatic dispersion compared to their DSP-based counterparts. We estimate conservatively that the high-speed analog electronics of an electrical PLL-based coherent receiver consume nearly 4 W for 200 Gbit/s DP-QPSK, assuming a 90-nm complementary metal-oxide semiconductor process.

This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital converter (TDC) and bang-bang phase detector (BBPD). The digital PLL's locking time can be reduced due to the multi-output comparing with the classical digital PLL's with standard BBPD. In order to further shorten the loop locking time, we propose to reuse the MSBs, which are trigged at the early stage of locking acquisition, such that the phase difference can quickly decrease. Because of its simple structure, the proposed DPLL can be designed without much effort. The prototype DPLL is fabricated in a standard 0.18-μm CMOS process. The measurement results show that the output clock frequency ranges from 0.768 to 1.344 GHz. The total measured power consumption is 4.7 mW and the measured locking speed is around 40 times faster than a typical design without reusing the MSBs at 1.024 GHz.

This paper presents a high dynamic range (DR) power-efficient voltage-controlled oscillator (VCO)-based continuous-time $\Delta \Sigma $ modulator. It introduces a robust and low-power fully-digital phase extended quantizer that doubles the VCO quantizer resolution compared to a conventional XOR-based phase detector. A tri-level resistor digital-to-analog converter is also introduced as complementary to the new quantizer, enabling high DR while creating a dynamic power saving mechanism for the proposed design. Fabricated in 130-nm CMOS, the analog-to-digital converter achieved peak Schreier Figure-of-Merit (FoM) of 174.3 dB with a high DR of 89 dB over 0.4-MHz BW, consuming only 1 mW under 1.2-V power supply. It also reaches a peak Walden FoM of 59 fJ/conv with 74.7-dB signal-to-noise-and-distortion ratio over 2-MHz BW.

This paper evaluates the capability of a broadband MEMS phase detector in the application of phase locked loops (PLLs) through the aspect of theory, measurement and modeling. For the first time, it demonstrates how broadband property and optimized structure are realized through cascaded transmission lines and ANSYS simulations. The broadband MEMS phase detector shows potential in PLL application for its dc voltage output and large power handling ability which is important for munition applications. S-parameters of the power combiner in the MEMS phase detector are measured with S 11 better than −15 dB and S 23 better than −10 dB over the whole X-band. Compared to our previous works, developed phase detection measurements are performed and focused on signals at larger power levels up to 1 W. Cosine tendencies are revealed between the output voltage and the phase difference for both small and large signals. Simulation approach through equivalent circuit modeling is proposed to study the PLL application of the broadband MEMS phase detector. Synchronization and tracking properties are revealed.

This paper reports recent progress in developing a new asynchronous digital phase comparator for the precision measurement of phase difference of voltage ratio devices and calibration of functional elements of phasor measurement units (PMUs) calibrator. The phase error of the proposed digital comparator is below 300 nrad at 50 Hz and 100 $\mu $ rad at 100 kHz with applied voltages ranging between 500 mV and 3 V, whereas the phase error of cables and connectors was estimated to be 4 $\mu \text{rad}$ at 1 MHz. Besides resistive dividers, the phase comparator has been employed for the characterization of frequency behavior of phase difference between the output and input of voltage and transconductance amplifiers for a PMUs calibrator. The system can also be an important tool for phase-frequency characterization of devices employed for specific wideband power measurements.

Using multiple notch filters (NFs) inside the control loop of a standard PLL is a basic strategy to improve its filtering capability. Often, adaptive NFs (ANFs) are employed for this purpose as they can block the disturbance components even under off-nominal grid frequencies. This advantage is at the cost of a rather considerable increase in the PLL implementation complexity and computational effort, particularly when ANFs have their own frequency estimation mechanism. The non-adaptive NFs (NNFs), contrary to ANFs, are easy to implement. They, however, have received a little attention in PLL applications. Therefore, their performance characteristics are rather unclear. To gain insight about the advantages and disadvantages of NNF-based PLLs (NNF-PLLs), analysis and design of these PLLs is conducted in this paper. This procedure includes: (1) selecting the appropriate number of NNFs inside the PLL control loop, (2) approximating dynamics of cascaded NNFs with a simple first-order low-pass filter, which simplifies the tuning procedure, (3) applying the symmetrical optimum method for selecting the control parameters of the NNF-PLL, and (4) performing extensive experimental results. The obtained results indicate that NNFs can sufficiently mitigate disturbances caused by the presence of harmonics in the PLL input while maintaining a fast dynamic response for the PLL. To be more exact, the NNF-PLL can provide a settling time around 2 cycle of the nominal frequency during phase and frequency jumps while having a peak-to-peak phase error less than 0.2° under a heavily distorted grid condition ( THD = 15%). It, however, may not be able to effectively reject the double-frequency disturbance component caused by the grid voltage unbalance. To deal with this problem, a hybrid combination of adaptive/nonadaptive NFs is suggested in this paper. The experimental results show that the resultant PLL, which is called the HNF-PLL, completely removes the grid voltage unbalance, effectively suppresses harmonics, and offers a fast dynamic response (a settling time around 1.5 cycle of the nominal frequency). The ease of implementation is kept in the HNF-PLL as only one of the NFs is adaptive and this NF does not require a separate frequency estimation mechanism.

This paper presents an all-passive negative feedback network that performs autonomous radio-frequency (RF) front-end beam-forming and dynamic beam-tracking toward the direction of the incident RF signal. The proposed feedback network consists of a passive RF signal processing network, voltage rectifiers, and voltage-controlled delay-line phased shifters, all of which are passive-only circuits. The negative feedback loop is realized by passive phase detection, phase-to-voltage conversion, and voltage-controlled phase shifting, achieving a large loop-gain and autonomous operation with zero DC power consumption. The nonlinear behavior of the loop is exploited to substantially expand the array field of view (FoV). A proof-of-concept broadband four-element all-passive self-steering beam-former at 5 GHz with a wide FoV is implemented in a standard 130 nm CMOS process. A high-quality four-element synthesized array factor is measured for the input progressive phase shift $\phi _{\mathrm {in}}$ from −180° to 180°. When the proposed negative feedback loop is enabled, the normalized array factor is −2.87/−2.8 dB at $\phi _{\mathrm {in}}= + 90^{\circ }$ /−90° with an input RF power $\text{P}_{\mathrm {in}}$ of −17 dBm/element at 5 GHz, achieving >25 dB array factor improvement over the open-loop operation. Moreover, the nonlinear feedback loop allows for significant array factor improvement even at $\phi _{\mathrm {in}} = +180^{\circ }$ /−180°. The proposed beam-former also achieves high-quality self-steering beam-forming from 4 to 5.68 GHz with 34.7% fractional bandwidth. Therefore, the proof-of-concept all-passive self-steering beam-former outperforms the state-of-the-art active designs in terms of beam-forming quality, FoV, and fractional bandwidth. To the best of the authors’ knowledge, this is the first demonstration of an all-passive negative feedback network for a broadband and wide FoV self-steering beam-forming with zero DC power consumption.

A four-port microwave phase detector based on MEMS power sensors at $X$ -band (8–12 GHz) is proposed in this paper. It consists of two power dividers, two power combiners, two phase shifters, and two MEMS power sensors. Four power dividers/combiners and two phase shifters compose a four-port junction to expand the phase detection range. A thermoelectric power sensor and a capacitive power sensor compose the MEMS power sensor for low and high power measurement. Two types of power sensors can improve the measurement range and enhance the overload capacity. This microwave phase detector is fabricated by GaAs monolithic microwave integrated circuit technology. Experiments show that its return loss is better than −10 dB, and the isolation is better than −13.2 dB over $X$ -band. Measured results of the phase shift fit well with the calculated results in an entire cycle of −180°~+180°. The phase detection sensitivities are $16.62~\mu \text{V}$ /° and 23.94 aF/°, and the response times are 0.408 ms and less than 20 ms for the two types of sensors, respectively. The dynamic range of phase detector can be expanded up to 4 W, which is almost quintuple our previous works.

To improve the disturbance rejection capability of phase-locked loops (PLLs), which are undoubtedly the most common synchronization tool in power and energy applications, using different filtering techniques have been suggested in the literature. Among these filtering strategies, the delayed signal cancellation (DSC) operator is highly popular probably because it can be easily tailored for different grid scenarios. The DSC operator(s) can be used either as an in-loop filter in the PLL structure or as a preprocessing filter before the PLL input. The latter case is often preferred mainly because it results in a faster dynamic response in the extraction of grid voltage parameters. In this paper, a combination of an adaptive DSC operator with multiple nonadaptive DSC operators is suggested as the PLL preprocessing stage. To compensate for the phase and amplitude errors caused by the nonadaptive operators, a compensator is designed and cascaded with them. The proposed filter requires a low computational burden for the implementation and ensures a fast dynamic response and high filtering capability for the PLL. The effectiveness of this technique is verified through experimental results.

Мета: Вібраційна інерціальна технологія є останньою з сучасних інерціальних технологій. Вона являє собою перспективний підхід до проектування інерціальних датчиків, який може бути використано для систем стабілізації та стеження, що експлуатуються на рухомих об’єктах широкого класу. Метою дослідження є розгляд переваг цієї технології у порівнянні з лазерною та волоконно-оптичною. Функціонування інерцального датчика на наземних рухомих об’єктах потребує деякого вдосконалення коріолісова вібраційного гіроскопа з метою спрощення обробки інформації, підвищення надійності та компенсації зміщення нуля. Методи дослідження: Вдосконалення коріолісова вібраційного гіроскопа полягає у введенні фазового детектора та додаткового блока збудження. Можливість використання вдосконаленого коріолісова вібраційного гіроскопа в системі стабілізації, що експлуатується на наземних рухомих об’єктах, показано на підставі аналізу вихідного сигналу гіроскопа. Ефективність використання коріолісова вібраційного гіроскопа в системах стабілізації підтверджується за допомогою методу імітаційного моделювання. Результати: Розроблено та проаналізовано схему коріолісова вібраційного гіроскопа, що містить фазовий детектор та додатковий блок збудження. Визначено спосіб компенсації зміщення нуля. Виконано моделювання системи стабілізації з вдосконаленим коріолісовим вібраційним гіроскопом. Отримано вирази для вихідних сигналів вдосконаленого коріолісова вібраційного гіроскопа. Виконано оцінку похибки вихідного сигналу та підтверджено можливість використання модифікованого коріолісова вібраційного гіроскопа в системах стабілізації. Представлено результати моделювання системи стабілізації та виконано їх аналіз. Висновки: Отримані результати підтверджують ефективність запропонованих рішень та можуть бути корисними для стабілізації платформ з приладовим обладнанням, що експлуатуються на рухомих об’єктах широкого класу.

IEEE This paper presents the theoretical and comparative analysis of two major time-based architectures for sensor interfaces. Both use a voltage-controlled oscillator (VCO) to achieve a highly-digital scalable implementation. The first architecture is based on a phase-locked loop, while the second one is count-based. Both systems are closed loop to efficiently mitigate the VCO nonlinearity. They show inherent first-order quantization noise shaping thanks to the use of an oscillator and phase detection. The two systems having a different working principle leads to different VCO requirements in terms of gain linearity (V-to-f or V-to-T linearity). Formulas are derived to predict the maximum SQNR for both architectures. Equations for the achievable maximum SNR taking into account the VCO phase noise are also derived, since this is the limit to the SNR in practical implementations. State-variable-based simulation results are presented, confirming the theoretical analysis and emphasizing the different design trade-offs and practical considerations. ispartof: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS vol:66 issue:7 pages:1114-1118 status: published

This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm2.

This brief presents a technique for compensating the bandwidth variation of digital phase-locked loops (PLLs) arising due to process, voltage and temperature (PVT) variation induced changes in loop parameters. For a digital PLL with a bang-bang phase detector, the bandwidth also depends on the phase noise level present at the input of the phase detector. The presented technique also compensates for the bandwidth variations induced by variations in phase noise power. The compensation technique is verified by a MATLAB model and transistor-level transient noise simulations.

Selected mapping (SLM) is a well-known method for reducing peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. However, as a consequence of implementing SLM, OFDM receivers often require estimation of some side information (SI) in order to achieve successful data recovery. Existing SI estimation schemes have very high computational complexities that put additional constraints on limited resources and increase system complexity. To address this problem, an alternative SLM approach that facilitates estimation of SI in the form of phase detection is presented. Simulations show that this modified SLM approach produces similar PAPR reduction performance when compared to conventional SLM. With no amplifier distortion and in the presence of non-linear power amplifier distortion, the proposed SI estimation approach achieves similar data recovery performance as both standard SLM–OFDM (with perfect SI estimation) and also when SI estimation is implemented through the use of an existing frequency-domain correlation (FDC) decision metric. In addition, the proposed method significantly reduces computational complexity compared with the FDC scheme and an ML estimation scheme.

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 ㎚ CMOS process, the proposed DLL occupies 0.0432 ㎟, and consumes 3.7 ㎽ from a 1.2-V supply at 2 ㎓.

This paper proposes a new fault ride-through (FRT) configuration for a fixed-speed induction generator-based–wind turbine (FSIG–WT). It utilizes a nine-switch converter (NSC) to enable shunt and series compensation in response to the system dynamics and grid faults. The steady-state control strategy and transient-management scheme are developed to ensure proper performance in steady-state, dynamic operation as well as enhanced FRT capability of the FSIG–WT. In addition to that, the developed control strategy tackles the balanced and unbalanced operation of the electric grid with an enhanced positive- and negative-sequence compensation control scheme. The recently reported grid synchronization scheme, namely, the frequency-locked loop (FLL) is implemented to achieve fast phase detection and transient response. Consequently, the performance of the FLL has been compared with the multiple reference–frame–phase-locked loop (MRF–PLL) to demonstrate its superior performance for enhancing transient response. The proposed topology, FLL, and control strategies are verified through a comprehensive simulation study to demonstrate the enhancement of the transient response and FRT capability of FSIG-WT in adherence to grid-code requirements.

A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).

The contact potential difference probes distinguished by great variety and produced mostly in the laboratory for specific experimental applications. As a rule, they consist of commercially available instrumentation, and have a number of disadvantages: large dimensions, complexity and high cost, small sensitivity, operating speed, noiseproof, etc. The purpose of this paper is to describe the basic approaches to design of the small dimension, complete contact potential difference probes, providing high sensitivity, operating speed, and noise immunity. In this paper the contact potential difference probe, which is a electrometer with dynamic capacitor plate at about 0.1–5 mm2 . These probes are could be used in scanning systems, such as a Scanning Kelvin Probe, as well as for controlling system of manufacturing processes, e.g. under friction. The design of such contact potential difference probes conducted using modern electronic components, unique circuitry and design solutions described in detail at paper. The electromechanical modulator applied for mechanical vibrations of the reference sample. To provide a high amplitude and phase stability the upgraded generator with Wien bridge was used instead traditional oscillation sensor. The preamplifier made on the base of modern operational amplifiers with femtoampere current input. The power of the preamplifier designed with «floating ground». It allows keeping the relation constant potential to the probe components when changing over a wide range the compensation voltage. The phase detector-integrator based on the electronic antiphase switches with the modulation frequency of the contact potential difference and the integrator. Fullwave phase detection would greatly increase the sensitivity of the probe. In addition, the application of the phase detection allows suppressing noise and crosstalk at frequencies different from the modulation frequency. The preamplifier and the reference sample mounted on a flexible printed circuit board and the edge mechanically connected with a vibrator. Modulator, phase detector-integrator, and other electronic components placed on a separate board. This design contributes to reduce the influence of electromagnetic interference and noise as well as removing microphonic effects, etc.

This paper describes a distributed sensing concept using coaxial cable-based Fabry-Perot interferometers (CCFPIs). Multiple reflectors are implemented along a coaxial cable, where every two consecutive reflectors can be considered as a low finesse CCFPI, which has a relatively weak reflection coefficient and insertion loss. The interferogram in a frequency domain of each individual CCFPI could be reconstructed through the proposed signal processing method, so that the phase detection could be applied to any CCFPIs on one cable to achieve high measurement accuracy. A large capacity sensor network with a relatively high measurement accuracy can be implemented simultaneously. The concept takes advantage of the time-domain multiplexing method and the pure frequency domain measurement, which is herein called a joint-time-frequency demodulation technique. Due to its effectiveness and robustness, the device is especially attractive for structural, downhole, or underwater applications.

The synthesis, design and analysis of a three-phase phase-locked loop (PLL) algorithm under grid voltage uncertainties is presented. Unlike other techniques, the proposed strategy is simple but yet, robust against unbalanced and distorted voltage conditions. The method does not rely on the symmetry of the three-phase voltages, like conventional PLL implementation techniques. Under phase lock, the reference voltage and the output voltage are in synchronism, hence they cross the zero axis at the same time. The proposed PLL implementation exploits this fact, by counting the difference between the zero crossing times of the grid voltage and the output voltage waveform, and generating an error signal proportional to this difference. This error is fed into a PI regulator which forces it to zero over time. The proposed algorithm is compared against two popular PLL techniques. Simulation and experimental results show better performance of the proposed PLL implementation in unbalanced grid voltage conditions.

This paper presents an innovative method to achieve the simultaneous phase control of multiple resonance frequencies of a linear multi-degree-of-freedom system using only one sensor/actuator pair. Each frequency is manipulated independently by means of a PLL-based control loop which comprises a digital averaging phase detector that combines the two most crucial tasks, namely the phase shift measurement and the frequency separation. The properties of the controller are designed individually for each mode using a linearized model of the control system. The method is applicable to all kinds of oscillators where frequencies near the structure’s natural frequencies are to be controlled. To validate the results experimentally, the controller is implemented on a digital signal processor (DSP) and applied to a torsional oscillator. Investigating two different damping conditions, the simultaneous control of five resonance frequencies of the oscillator illustrates the effectiveness and stability of the multiple frequency tracking. The method is able to significantly improve the accuracy and versatility of sensor applications. As an example a method is presented that enables the direct determination of the modal damping by using two frequencies corresponding to one single vibration mode.

This paper presents an equivalent-circuit model of a MEMS phase detector and deals with its application in phase-locked loops (PLLs). Due to the dc voltage output of the MEMS phase detector, the low-pass filter which is essential in a conventional PLL can be omitted. Thus, the layout area can be miniaturized and the consumed power can be saved. The signal transmission inside the phase detector is realized in circuit model by waveguide modules while the electric-thermal-electric conversion is illustrated in circuit term based on analogies between thermal and electrical variables. Losses are taken into consideration in the modeling. Measurement verifications for the phase detector model are conducted at different input powers 11, 14 and 17 dBm at 10 GHz. The maximum discrepancies between the simulated and measured results are 0.14, 0.42 and 1.13 mV, respectively. A new structure of PLL is constructed by connecting the presented model directly to a VCO module in the simulation platform. It allows to model the transient behaviors of the PLL at both locked and out of lock conditions. The VCO output frequency is revealed to be synchronized with the reference frequency within the hold range. All the modeling and simulation are performed in Advanced Design System (ADS) software.

In modern warfare, communication carrier frequency of opponent's communication radar should be frequently measured, so as to make demodulation and obtain its binary communication information for declassification. To make demodulation on opponent's communication signal, certain method must be adopted to estimate the frequency of such communication microwave signal. Therefore, the measurement of the frequency of unknown microwave signal is an important application in military warfare. In this study, a new microwave frequency measurement method is proposed based on the detection of unknown microwave signal's phase shift. Theoretical analysis has been made. The formula of theoretical derivation can prove the feasibility of the project. Relevant experimental verification has been conducted. The final experiment in this study also proves the practicality and feasibility of the method.

International audience; Phase noise is an important parameter to characterise the frequency stability of oscillators and synthesised signal generators. Accurate measurement of phase noise is required for various applications in radar, communication and navigation systems. A single-channel phase-detector based phase noise measurement system is described. The system’s measurement errors and uncertainties have been analysed in details. The expanded uncertainty is about 2.7 dB for calibrating phase noise of a signal generator at 0.001–1.6 GHz for frequency offsets from 1 Hz to 100 kHz. The uncertainty budget for measuring a signal generator’s phase noise at 640 MHz is also presented.

With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase-locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented. By sensing the supply noise using an analog-to-digital converter (ADC), an observer–controller loop filter jointly processes the ADC and phase detector outputs to determine the oscillator control signals that minimize the output jitter. The proposed digital PLL is shown to be significantly more robust to supply noise compared with a conventional PLL.

International audience; The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory.

The phase-locked loop circuit PLL cycle-slips CS phenomenon is a problem in two-level baseband clock and data recovery CDR data-synchronization. A singular example is that of a CDR synchronizer that uses a PLL in cascaded with delay-lock-loop P/DLL architecture. The CS issue is most evident when testing jitter-tolerance to sine-modulated jitter, particularly for sine-modulated jitter-frequencies near the PLL bandwidth. Reuse of a bang-bang frequency-detector, already on board of reference-less CDRs, does CS detection and provides for suppression producing a clean demodulation. In the cascaded-DLL of Rhee's P/DLL [1], this CS-suppressed PLL-clock assures proper DLL operation to broadband the jitter-tolerance recommendation of the synchronous optical network SONET. Copyright © 2016 John Wiley & Sons, Ltd.

The basics, design, prototype and characterization of a microwave based linear displacement sensor for piston position detection in hydraulic cylinders is presented. This function is important for industrial applications to provide a precise feedback in position controlled hydraulic drives. At present technologies for piston position detection have disadvantages and are cost-intensive. Used technologies are inductive, magnetostrictive, magnetic or mechanical and have the need for design modifications in the cylinder structure, limited robustness and life-time. Microwave technology is established in many fields e.g. communication, traffic radar or air-defence radar. In this paper we describe a minimally invasive and contactless implementation of this technology for hydraulic drives. The development of an industrial sensor has raised new challenges and lead to new sensing concepts. Finally our solutions, designs and test results are presented.

In this paper, a new phase locked loop (PLL) is proposed for both single and three phase systems. A Phase detection is the most challenging issue in single phase PLLs. Due to the benefits of vector multiplier phase detector, new orthogonal signal estimator is proposed with the help of simple VCO to make the vector multiplier PD usable for single phase PLLs. The proposed PLL shows fast dynamic response and robust performance against input signal distortion such as harmonic polluted and amplitude collapse. Also, it has a simple structure and less computational burden which make it easy for fully digital implementation. The proposed PLL is implemented digitally based on a TMS320F28335 developed board. To fully evaluate the performance of proposed PLL, a 4 kW single phase grid connected converter is also provided. All the simulation and experimental results verify the effectiveness and superior performance of the proposed PLL.

In this paper, a new reactive power and harmonic compensation procedure based on the variable forgetting factor-recursive least squares (VFF-RLS) estimator and new phase-locked loop is proposed. For this purpose, the fundamental harmonic component of load current is estimated with VFF-RLS. Independence on order and amplitude of harmonics, fast dynamic and high accuracy are the remarkable features of the designed estimator. As in the case of load changes, the sag/swell and phase jump in grid voltage, optimal compensation is performed in less than half a cycle with a low total harmonic distortion value. In addition, to compensate for an infected power system by varied frequency, a second-order general integrator-frequency-locked loop (SOGI-FLL) control system based on wavelet transform (WT) has been proposed. This phase detector can track the reference phase of a grid in the best manner in the presence of frequency variations. The effectiveness of the proposed method in a single-phase power system has been validated using both simulation and experimental results.

All mechanical structures are subjected to deformation and cracks, due to fatigue, stress, and/or environmental factors. It is, therefore, of uttermost importance to monitor the mechanical condition of critical structures, in order to prevent catastrophic failures, but also to minimize maintenance costs, i.e., avoid unnecessary inspections. A number of technologies and systems can be used for this purpose: among them, the ones proposing the use of wireless passive crackmeters have a strong impact potential, in terms of simplicity of installation and measurement and low cost. This paper, hence, shows a crack width wireless radio-frequency identification sensor, developed for applications on various materials (such as concrete and metal) and able to detect submillimeter deformations occurring on the object, on which it is placed. A design method based on high-sensitivity phase detection is shown.

This work describes an electrical interferometer for contactless permittivity measurements working at 120 GHz. It was fabricated in a 130 nm SiGe process featuring an ft and fmax of 240 and 330 GHz. The on-chip system contains a 120 GHz VCO with a tuning range of 7 GHz featuring a divide-by-64 circuit to enable external PLL operation. The subsequent buffer provides 7 dBm of output power at 120 GHz. Additionally, the IC contains high-precision and high-resolution phase shifters based on a slow-wave transmission line approach with digital control for direct readout ability. A 120 GHz LNA with 17 dB gain and a power detector to provide DC output signals were realized on chip. It enables sample emulation capability by phase shift inducement in the measurement as well as a reference transmission line. In terms of phase detection, the system shows a sensitivity of 907.36 MHz/°.

In this paper, an impedance sensor which is an easy to use constant phase element (CPE) is used with an aim of detection and automation of fruit juice adulteration. As the ionic property of the adulterated fruit juice changes, so does the impedance sensor's constant value phase angle. The conditioned output from the sensor by a phase detector circuit converted into the respective voltage level informs us about adulteration that should remain constant for some range of frequencies. This conditioned output is later sent to an Arduino which has been programmed to identify adulteration with the change in voltage value and opens or closes the valve accordingly. By applying a coating of poly-methyl-meth-acrylate (PMMA) film the sensor is made bio-compatible, thus making it suitable for this application.

© The Institution of Engineering and Technology 2018. A fully-voltage-controlled oscillator (VCO)-based continuous-time (CT) Delta-Sigma (ΔΣ) analogue-to-digital converter (ADC) is reported, implementing second-order noise shaping without any analogue integrators. Traditional power-hungry front-end analogue integrator is replaced by a highly-digital power-efficient VCO-based integrator, which is constructed by a VCO, a phase detector and a charge pump. The quantisation is executed by a VCO-based quantiser with intrinsic noise shaping. Taking advantage of the mostly-digital and high-order structure, a spurious-free dynamic range of 74 dB and a figure-of-merit of 52 fJ/step over a 40 MHz bandwidth are achieved by a 0-2 multi-stage shaping (MASH) demonstration in 40 nm CMOS. ispartof: ELECTRONICS LETTERS vol:54 issue:17 pages:1018-1019 status: published

Author(s): Xu, Y; Huang, G; Doolittle, L; Du, Q; Wilcox, R; Yang, J; Lin, Z; Du, Y; Yan, L; Huang, W; Tang, C | Abstract: High-precision phase detection is critical to the timing and synchronization system for particle accelerators. A live calibration signal is introduced to femtosecond-level phase detection in order to measure the relative phase jitter between a reference wave and a radio frequency (RF) signal, and compensate for the cable electrical length drift due to the thermal variation effect. Non-IQ sampling and 2-stage cascaded integrator-comb filters are integrated into the field-programmable gate array-based digital signal processing to reduce spectrum aliasing and suppress noise. Fine adjustment of hardware components has been made to ensure the isolation between different signals and the linearity over the full-range power level. We have achieved a 6.3 fs root mean square timing jitter for a 2856 MHz RF signal in a single channel, compared to the theoretical limit of 5.1 fs for the current hardware component.

Magnetic induction spectroscopy (MIS) has many potential applications in medical engineering as well as industrial and food manufacturing process applications, providing a contact-less impedance measurement. However, the applications of MIS is currently limited due to the high precision of phase detection required over a wide band of frequencies. This paper focuses on phase detection aspect of the MIS. The chosen phase detection method is investigated in depth and a prototype hardware and software is developed. The phase detection system is then tested and compared to other recent MIS system design. The prototype hardware is able to measure the phase difference of signals from 200 kHz to 20 MHz with milli-radian precision which will significantly enhance the MIS systems.

Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.

This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.

In many phase-lock loop (PLL) applications, the naturally occurring pull-in process is too slow and unreliable. Therefore, PLLs use acquisition aids to mitigate the process of locking onto the phase of some input reference signal. Commonly used acquisition aids have deficiencies with limiting effects. For voltage-controlled oscillator (VCO) sweeping, deficiencies include lock detector requirements and search rate limitations. For a charge-pump subsystem, the operated sequential phase detector (PD) is less resistant to errors than an analog multiplier PD. In order to overcome the deficiencies of common acquisition aids and improve PLL robustness to perturbations, it is proposed to use a conventional or a second order sliding mode controller (SMC/2-SMC) as an acquisition aid to provide robust finite-time phase-lock in the PLL. This improvement is achieved without the use of a lock detector, and the disabling of the acquisition aid is not necessary. The PLL aided by SMC/2-SMC is studied analytically and via simulations. A significant improvement of the PLL’s performance is demonstrated; specifically, the lock time is decreased, and the steady state phase error is reduced for a frequency ramp input.

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used, thanks to their high efficiency at high frequencies. The initial specifications driving this study require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip (PLL) a dead-time generator and a phase detector. The PA was designed in a 0.18- $\mu$ m CMOS high-voltage process technology and occupies an area of 9.86 mm $^2$ . It works at frequencies up to 14 MHz and 30-V supply and efficiencies higher than 80 $\%$ are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimizes power delivery to medical implants.

For a low-stiffness beam driven by a ball-screw stage, the lateral vibrations cannot be adequately controlled by a collocated compensator based on rotary-encoder feedback alone. Acceleration signals at the tip of the flexible beam are measured for active vibration control in addition to the collocated compensator. A second-order bandpass filter (a line enhancer) and two notch filters are included in the acceleration-feedback loop to raise modal dampings for the first and the second flexible modes without exciting higher-frequency resonances. A novel adaptation algorithm is devised to tune the center frequencies of the notch filters in real time. It consists of a second-order low-pass filter, a second-order bandpass filter and a phase detector. Improvement of the control system is elaborated progressively with the root-locus and bode-plot analyses, along with a physical interpretation. Extensive testings are conducted on an experimental device to verify the effectiveness of the control method.

This paper proposes an automatic resonant frequency tracking scheme for resonant converters. A plant modeling approach is presented based on realistic ramp variation of resonant frequency due to slowly varying environmental conditions. The drift in resonant frequency is detected by observing the phase relationship of an electrical variable pair. A rigorous analysis is carried out to select the most suitable variable pair for phase comparison. The effects of circuit nonidealities on the proposed phase detection technique have been detailed. The proposed control technique has been implemented using low cost analog circuitry and is applied to a parallel LLC tank-based resonant boost dc-dc converter. Experimental results are presented on a 160-W prototype to validate the analytical predictions.

This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with fT = 200 GHz. The PLL is intended to be used for beam steering in an 81---86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals ?115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals ?100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers.

We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be programmed by scanning the dead-zone width of a variable dead-zone BBPD in the time domain. Its linear-like gain characteristics result in less sensitive CDR performance against input jitter and process, voltage, and temperature (PVT) variations. In addition, a built-in on-chip jitter monitor can be easily implemented using our ML-BBPD. A prototype 1.25-Gb/s CDR based on our ML-BBPD with a built-in jitter monitor is realized with 0.18- $\mu{\rm m}$ CMOS technology and its performance is successfully verified with measurement.

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

This paper presents a grid synchronization method based on the implementation of sliding Goertzel discrete Fourier transform (SGDFT). The conventional phase locked loop (PLL) exhibits large phase error, be difficult to implement, and their performance is also indistinct under conditions where the grid frequency varies or the supply is distorted with high frequency harmonics. In the proposed SGDFT show a robust phase tracking capability with fast transient response under distorted grid conditions. The sampling frequency is adjusted to correct the phase errors by the SGDFT filter whenever variation in the frequency or harmonics.