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In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. 4×4 multipliers have been designed in a 45nm predictive technology using the proposed SG-SCL gates and pipeline structure and using the conventional MTNCL (Safe SECRII architecture), and they have been compared in terms of speed, power consumption, energy and size. The simulation results show that the proposed design reduces 60% energy, 54% leakage power and 25% area compared to the MTNCL (Safe SECRII architecture) design.

Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.

This paper proposes presents a low power and high-speed four-quadrant analog multiplier in the current mode based on dual translinear loops using 32nm CMOS and 32nm CNTFET technologies to investigate and compare the performance differences of the analog circuits on CNTFET technology and CMOS 32nm technology nodes. All the simulations were performed using hspice with 32nm CMOS from PTM library and 32nm CNTFET from Stanford University technologies at the same power supply level. CNTFET based multiplier shows a wider linearity over considerable range of outputs (−10 μA to +10μA) while the CMOS based multiplier shows (−7μA to +7μA) and the 3db frequency of the CNTFET based multiplier is 110GHz while the 3dB frequency of the CMOS based multiplier is only 2.45GHz.

This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.

This paper presents an area efficient 3-tap speculative Decision Feedback Equalizer (DFE) with a novel current-integrating summer for data self correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. In this paper, a novel area efficient DFE is proposed where the four summers are reduced to two. By using switched-capacitors to separate the first speculative tap, two parallel paths for speculation can be driven by a single summer. The proposed DFE consumes 17.4 mW with 1.8V supply when equalizing 4Gb/s data passed over a channel with 28 dB loss at 2GHz.

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method"s accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

Ubiquitous network and wireless sensor networks is being applied in various fields. Located at target areas, node of wireless sensor network uses batteries as a power source. Batteries have a limited energy in sensor network applications. Also, before use, the battery must be charged and It is difficult to replace the battery. Therefore, energy harvesting technology is being researched and being developed for long life of sensor node. Especially, sola energy is being extensively researched. because that can have great amounts of energy than other environmental energy in a short time. In this study, we tested battery charging and recharging, operation of sensor node using Solar Cell. Also, monitoring data gathering and voltage Analysis showed energy harvesting time of Sola Cell battery for sensor node and operation of sensor node.

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

This article describes a novel technique for analysing the effects of supply voltage noise on circuit delay for VLSI circuits. Scattering parameters are used to model the supply voltage variation in the frequency domain and to reduce the original power grid and simulation time. The interconnections of the power grid are modelled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOSFET modelling method for a static timing analyser is proposed based on the power grid analysis. A MOSFET logic is modelled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimisation problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45 nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of V DD and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

This paper presents a novel statistical characterization for accurate timing and a new probabilistic-based analysis for estimating the leakage power in partially depleted silicon-on-insulator (PD-SOI) circuits in 100-nm BSIMSOI3.2 technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI complementary metal-oxide-semiconductor (CMOS) circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fan-out effect, along with a new input-independent method for estimating the leakage power based on a probabilistic approach. The proposed timing and leakage power estimate algorithms are implemented in MATLAB, HSPICE, and C. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5%, compared with random simulation results.

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

Internet of Everything (IoE), embedded with microcontrollers and wireless technologies onto a single system on a chip (SoC), are able to be connected with other devices in the cloud. Wearable sensors and RFID are core technologies in IoE. Energy efficiency and miniaturization are the two most critical technical challenges for the hardware implementation of microelectronic systems enabling Internet of Everything. Low-power smart systems on a chip are the key enabling solutions. In this paper, we outline the key hardware components and design challenges of BSN.

In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration is proposed for digital controlled DC-DC converters. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

This paper presents a CMOS neuron circuit design based on the Hindermarsh-Rose (HR) neuron model. In order to be fabricated in a 0.18㎛ CMOS technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This on chip solution also minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. Simulation results demonstrate that the proposed CMOS neuron performs the expected waveform with time and amplitude scaled. The chip was fabricated by MagnaChip with an active die area of 1.1㎟ including I/O pads. The experimental results validate the performance of this CMOS neuron.

A design and integration of highly accurate Parametric Measurement Unit (PMU) with 600MHz Driver, Comparator, and an Active Load (DCL) is presented in this paper using 0.5um BiCMOS process. These circuits are necessary components of Automated Test Equipment (ATE) systems used to test ICs and are often referred to collectively as the Pin Electronics (PE). PMUs are high accuracy low bandwidth circuits that have to drive a range of capacitive loads. The need for high accuracy requires the use of feedback and high gain operational amplifiers. The trade-offs to be made in these circuits is between accuracy and settling time. Better accuracy requires higher gain which requires more aggressive compensation which increases settling time. A design approach that strikes a balance between DC accuracy and settling time is proposed. Design techniques are used to minimize the output capacitance of the PMU allowing its integration onto the 600MHz DCL in the circuit that affect the speed of the test path. The measured data from the fabricated chip shows the minimum open loop gain of 42dB for desired linearity error with 600pF capacitor pole compensation capacitor in high current range. The design has been successfully integrated on 1580um by 600um BiCMOS silicon area with less than 150uV measured voltage error and less than 0.001% measured current error.

As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown (also called time dependent dielectric breakdown (TDDB)) has become a major reliability concern. The oxide breakdown is categorized into hard breakdown (HBD) and soft breakdown (SBD). With the present of HBD and SBD, it is difficult to control the ON current of the MOSFET device. Especially, HBD causes a catastrophic failure of the device and the entire circuits. In this paper, the TDDB effects on the delay and power of the nanoscale CMOS circuits are analyzed using ISCAS85 benchmark circuits, which are designed using a 45-nm CMOS predictive technology model. Based on the TDDB analysis, a new hard breakdown monitoring circuit has been proposed.

This paper presents a novel fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports programmable regulated load voltage ranging from 2.6V to 3.2V out of 5V input supply. MOS capacitors are used for flying capacitors (600pF) and load capacitor (400pF) in this implementation. To minimize the bottom-plate parasitic capacitor related loss while maximizing the load current driving capability, the proposed 4-to-3 step-down topology utilizes two differently sized conventional 2-to-1 step-down topologies, each of which has different value of flying capacitor. In addition, the proposed implementation reduces switching loss and control circuit loss since the internally generated output voltage of the bottom 2-to-1 block is used as the supply for the control circuits throughout the small internal LDO regulator. The proposed converter is designed and simulated using high-voltage 0.35µm BCDMOS technology. The programmable output voltage is regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift register and digitally controlled oscillator (DCO). The proposed switched-capacitor converter achieves the peak efficiency of 72% while it delivers the load current between 1mA and 10mA. 10-phase interleaving technique enables the output voltage ripple of the load voltage to be less than 1%.

This paper presents the all-digital phase-locked loop (ADPLL) with the local passive interpolation time-to-digital converter (LPI-TDC). Unlike the conventional LPI-TDC, the proposed TDC has a tristate inverter delay cell in only first delay chain, other delay cell is composed of only normal inverters that have same delay as tristate inverter. LPI-TDC based a tristate has the advantages of higher resolution than conventional LPI-TDC. The resolution of the proposed LPI-TDC increases by approximately 1.5 times compare to the conventional LPI-TDC. The proposed ADPLL has been implemented using 0.18µm CMOS process. The peak to peak jitter is 32.86ps, and the power consumption of the ADPLL is 25.02mW, which is lower than the conventional ADPLL, at 600 MHz operation with 1.8V power supply voltage.

A design approach of a Parametric Measurement Unit (PMU) is presented along with integration onto the same Integrated Circuit (IC) with 600MHz Driver, Comparator, and Active Load (DCL). These circuits are necessary components of many Automated Test Equipment (ATE) systems used to test ICs and are often referred to collectively as the Pin Electronics (PE). PMUs are high accuracy and low bandwidth circuits that have to drive a range of capacitive loads. The need for high accuracy requires the use of feedback and high gain operational amplifiers. The tradeoff to be made in these circuits is between accuracy and settling time. Better accuracy requires higher gain which requires more aggressive compensation which increases settling time. A design approach will be proposed that strikes a balance between DC accuracy and settling time. In areas of the circuit that affect the speed of the test path, novel design techniques are used to minimize the output capacitance of the PMU allowing its integration onto the 600MHz DCL.

Skin sensor is the most critical part for controlling robot sensing behavior. In this paper, we provide circuit implementation and simulation for sensing the pressure in the skin sensor using CMOS and CNFET at 32nm technology node. The proposed scheme can be used as an active matrix like memory element in the skin sensor and it is demonstrated by showing the output image according to the skin sensor's pressure location using Matlab implementation. The circuits are compared with CMOS and CNFET (Carbon Nanotube FET) at different supply voltages to show the feasibility of the scheme. Also, low-leakage circuit technique is applied to the proposed sensing circuit.

This paper proposes a new design of carbon nanotube FETs (CNFETs) based SRAM cell operating in subthreshold region. By using optimum back-gate biasing scheme for each transistor, the proposed SRAM cell achieves the best overall performance considering noise margin, delay and power. Compared with traditional subthreshold CNFET SRAM cell, the proposed SRAM cell increases static voltage noise margin (SVNM) 36%, increases static current noise margin (SINM) 2.5X, and reduces delay 61% with power consumption increasing only 1% for read operation. For write operation, the proposed SRAM cell increases write noise margin (WNM) 2.5X and reduces power consumption and delay 17% and 56% respectively compared with traditional subthreshold CNFET SRAM cell. In terms of total number of nanotubes (area) of CNFET SRAM cell, the proposed subthreshold CNFET SRAM cell can reduce at least half of total number of nanotubes without compromising noise margin, power and delay. New CNFET SRAM cell structure is proposed to dynamically bias each transistor at different operation modes.

This paper presents the hot-carrier-injection (HCI)-induced delay degradation of the power gating structure as well as the HCI impact on critical issues in the power gating, such as leakage power, wake-up time, and wake-up rush-current. Considering this HCI impact, a novel adaptive HCI-aware power gating structure is proposed to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the HCI effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new HCI monitoring circuit, which is imperative for a good adaptive technique. The simulation results are compared to those of power gating without the adaptive technique and show that both the circuit-delay and wake-up time dependence of the power gating structure on the HCI stress is minimized with only 2% and 3% increase, respectively while keeping small leakage power and rush-current. The proposed technique is evaluated using ISCAS85 benchmark circuits which are designed using 45nm CMOS predictive technology model.

This paper presents a novel probability based analysis for leakage power estimation of partially-depleted silicon-on-insulator (PD-SOI) circuits. The proposed leakage power estimation algorithms is implemented in C language, and the proposed methodology is tested by ISCAS85 benchmark circuits designed in 100 nm SOI technology. The results show that the error is within 4% compared with Hspice Monte Carlo simulation results.

PWAM transmitter combines pulse width modulation (PWM) and pulse amplitude modulation (PAM) together to boost the performance of the high speed serial link transceiver. In this paper, two PWAM transmitter architectures are proposed and the performances of them are compared based on the power consumption analysis of the drivers. Bipolar driver is an energy efficient choice for the PWAM scheme. It can save more than half of the driver power consumption. The correct clock scheme for phase selector is also discussed in this work.

A fully digital self-adjusting high efficiency power supply system has been developed based on an FSM control scheme. The system dynamically monitors circuit performance with a slacktime detector, and provides a substantially constant minimum-supply voltage for digital processors to properly operate at a given frequency with regard to different process-voltage-temperature (PVT) and load conditions. The digital FSM scheme significantly reduces the complexity of control loop implementation (

This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, the control system determines the optimal trade-off between supply voltage and the forward body bias voltage to satisfy the performance requirement. In the standby mode, a new optimal body-bias technique in nanoscale CMOS technology is implemented to monitor subthreshold, gate tunneling, and band-to-band tunneling leakage current and reduce leakage current by optimal substrate bias voltage(forward of reverse biasing). The optimal body bias control system reduces the leakage current by up to 1000 times for ISCAS85 benchmark circuits designed using 32nm CMOS technology