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We developed a measurement and evaluation scheme to perform dispersion analysis on arbitrarily cut orthorhombic crystals based on the schemes developed for triclinic and uniaxial crystals. As byproduct of dispersion analysis the orientations of the crystal axes are found. In contrast to the spectra of arbitrarily cut uniaxial crystals, where the fit routine has to separate two independent principal spectra, the spectra of arbitrarily cut orthorhombic crystals are a combination of three independent spectra and the evaluation scheme gets more complex. Dispersion analysis is exemplary performed on two different crystals, which show different spectral features and different levels of difficulties to evaluate. Neodymium gallate (NdGaO3) has broad overlapping reflections bands while topaz (Al2SiO4 [F, OH]2) has a quite high total number of infrared active bands.

Small wustite (Fe1−xO) crystals were grown using the micro-pulling-down technique. Eutectoid decomposition of the grown crystals was suppressed by fast cooling associated with fast crystal pulling at a rate of 50 mm/min. Crystals grown at lower rates contained magnetite as a second phase indicating the beginning decomposition. Additionally, in those crystals the original wustite of near-eutectoid composition ( x ≈ 0.05 ) was decomposed into two wustite phases of which one was iron-poor, x ≈ 0.09 , the other instead iron-rich, near-stoichiometric, x ≈ 0.02 .

In the course of development of transparent semiconducting oxides (TSOs) we compare the growth and basic physical properties bulk single crystals of ultra-wide bandgap (UWBG) TSOs, namely β-Ga2O3 and Ga-based spinels MgGa2O4, ZnGa2O4, and Zn1-xMgxGa2O4. High melting points of the materials of about 1800 -1930 °C and their thermal instability, including incongruent decomposition of Ga-based spinels, require additional tools to obtain large crystal volume of high structural quality that can be used for electronic and optoelectronic devices. Bulk β-Ga2O3 single crystals were grown by the Czochralski method with a diameter up to 2 inch, while the Ga-based spinel single crystals either by the Czochralski, Kyropoulos-like, or vertical gradient freeze / Bridgman methods with a volume of several to over a dozen cm3. The UWBG TSOs discussed here have optical bandgaps of about 4.6 - 5 eV and great transparency in the UV / visible spectrum. The materials can be obtained as electrical insulators, n-type semiconductors, or n-type degenerate semiconductors. The free electron concentration (ne) of bulk β-Ga2O3 crystals can be tuned within three orders of magnitude 1016 - 1019 cm−3 with a maximum Hall electron mobility (μ) of 160 cm2V−1s−1, that gradually decreases with ne. In the case of the bulk Ga-based spinel crystals with no intentional doping, the maximum of ne and μ increase with decreasing the Mg content in the compound and reach values of about 1020 cm−3 and about 100 cm2V−1s−1 (at ne > 1019 cm−3), respectively, for pure ZnGa2O4.

The best hope for reducing long-standing global climate model biases is by increasing resolution to the kilometer scale. Here we present results from an ultrahigh-resolution non-hydrostatic climate model for a near-global setup running on the full Piz Daint supercomputer on 4888 GPUs (graphics processing units). The dynamical core of the model has been completely rewritten using a domain-specific language (DSL) for performance portability across different hardware architectures. Physical parameterizations and diagnostics have been ported using compiler directives. To our knowledge this represents the first complete atmospheric model being run entirely on accelerators on this scale. At a grid spacing of 930 m (1.9 km), we achieve a simulation throughput of 0.043 (0.23) simulated years per day and an energy consumption of 596 MWh per simulated year. Furthermore, we propose a new memory usage efficiency (MUE) metric that considers how efficiently the memory bandwidth – the dominant bottleneck of climate codes – is being used., Geoscientific Model Development, 11 (4), ISSN:1991-9603, ISSN:1991-959X

The paper is devoted to theoretical end experimental studies of the low-frequency Self-excited Acoustical System (SAS), which allows monitoring stress changes in various elastic media including metals, concrete and mass rocks. The main principle of the SAS system is using a vibration exciter and vibration receiver placed on a sample with a positive feedback, which causes the excitation of the system. Stress changes manifest themselves in small but detectable variations of resonance frequency which can be used to indirectly measure stress changes in the material. In the paper the considerations concerning working frequency of SAS were performed. It was suggested that in the case of stress variation in mass rock monitoring, the low frequency (even infrasound) band should be selected, in contrast to the stress monitoring in columns of marble or concrete, where frequencies from an acoustic band should be used. Computer simulations conducted in the MATLAB-Simulink environment were based on the research performed in the laboratories. They focused on finding a relationship between the compressing force and velocity of sound in a specimen made of concrete. Results of the simulations allowed to state that the frequency of self-excited oscillations of simulated SAS change linearly with the pressing force. In the next step the laboratory experiments were carried out. The impact on stress measurement parameters such as: the position of sensors, actuator, and the influence of geometrical shape and dimensions of the sample. A sample of sandstone compressed in a frame by a hydraulic press was used in the study. The results proved the applicability of the design system. Additionally, the new possible applications of SAS were suggested, such as monitoring stress variations of stresses in mass rock, particularly in the active seismic zones.

Terbium titanate (Tb$_2$Ti$_2$O$_7$) is a spin-ice material with remarkable magneto-optical properties. It has a high Verdet constant and is a promising substrate crystal for the epitaxy of quantum materials with the pyrochlore structure. Large single crystals with adequate quality of Tb$_2$Ti$_2$O$_7$ or any pyrochlore are not available so far. Here we report the growth of high-quality bulk crystals using the Czochralski method to pull crystals from the melt. Prior work using the automated Czochralski method has suffered from growth instabilities like diameter fluctuation, foot formation and subsequent spiraling shortly after the seeding stage. In this study, the volumes of the crystals were strongly increased to several cubic centimeters by means of manual growth control, leading to crystal diameters up to 40 mm and crystal lengths up to 10 mm. Rocking curve measurements revealed full width at half maximum values between 28 and 40" for 222 reflections. The specific heat capacity c$_p$ was measured between room temperature and 1573 K by dynamic differential scanning calorimetry and shows the typical slow parabolic rise. In contrast, the thermal conductivity \kappa(T) shows a minimum near 700 K and increases at higher temperature T. Optical spectroscopy was performed at room temperature from the ultraviolet to the near infrared region, and additionally in the near infrared region up to 1623 K. The optical transmission properties and the crystal color are interpreted to be influenced by partial oxidation of Tb$^{3+}$ to Tb$^{4+}$., Comment: 7 pages, 7 figures, accepted for CrystEngComm

This paper reports a follow-up feasibility study on different approaches for numerical modeling of blast loads, implemented recently in a few commercial programs based on finite element method and explicit time integration. Four approaches have been considered including: explicit blast wave representation using fluid-structure interaction (FSI) with 2D and 3D multi-material arbitrary Lagrangian-Eulerian (ALE) formulations, direct application of empirical explosive blast loads on structures, and the most recent, combined method, in which direct empirical loading is applied to a reduced ALE domain. Each of these approaches has its own strengths and weaknesses, although the last one seems to be the most universal. Based on the published experimental data, a benchmark problem was selected, which considers a pressure loading exerted by explosion of near field hemispherical charges on a rigid steel plate. The comparison is done in terms of pressure peaks (overpressure) and time histories of reflected pressure, and reflected specific impulses.

Truly bulk ZnGa2O4 single crystals were obtained directly from the melt. High melting point of 1900 ± 20 °C and highly incongruent evaporation of the Zn- and Ga-containing species impose restrictions on growth conditions. The obtained crystals are characterized by a stoichiometric or near-stoichiometric composition with a normal spinel structure at room temperature and by a narrow full width at half maximum of the rocking curve of the 400 peak of (100)-oriented samples of 23 arcsec. ZnGa2O4 is a single crystalline spinel phase with the Ga/Zn atomic ratio up to about 2.17. Melt-grown ZnGa2O4 single crystals are thermally stable up to 1100 and 700 °C when subjected to annealing for 10 h in oxidizing and reducing atmospheres, respectively. The obtained ZnGa2O4 single crystals were either electrical insulators or n-type semiconductors/degenerate semiconductors depending on growth conditions and starting material composition. The as-grown semiconducting crystals had the resistivity, free electron concentration, and maximum Hall mobility of 0.002–0.1 Ωcm, 3 × 1018–9 × 1019 cm−3, and 107 cm2 V−1 s−1, respectively. The semiconducting crystals could be switched into the electrically insulating state by annealing in the presence of oxygen at temperatures ≥700 °C for at least several hours. The optical absorption edge is steep and originates at 275 nm, followed by full transparency in the visible and near infrared spectral regions. The optical bandgap gathered from the absorption coefficient is direct with a value of about 4.6 eV, close to that of β-Ga2O3. Additionally, with a lattice constant of a = 8.3336 Å, ZnGa2O4 may serve as a good lattice-matched substrate for magnetic Fe-based spinel films.

Results from experimental testing of three permit vehicles are presented in the paper. The selected heavy vehicles, which require permits from state DOTs, included two tractor-trailer systems and a midsize crane. The vehicles were experimentally tested on popular existing speed bumps and on a representative highway bridge. The selected bridge was a reinforced-concrete structure constructed in 1999, located on the U.S. 90 in Northwest Florida. The bridge approach depression, combined with a distinct joint gap between the asphalt pavement and the concrete deck, triggered significant dynamic responses of the vehicle-bridge system. Similar dynamic vibrations were observed and recorded when the permit vehicles were driven over the speed bumps. Time histories of relative displacements, accelerations, and strains for selected locations on the vehicle-bridge system were recorded. The analysis of experimental data allowed for assessment of actual dynamic interactions between the vehicles and the speed bumps as well as dynamic load allowance factors for the selected bridge.

Channel group delay distortion represents the transmission channel's phase dispersion, which results in signal distortion and adds intersymbol interference (ISI) to the received data eyes in addition to amplitude attenuation. Despite the fact that channel group delay distortion is especially critical in high-speed backplane applications, its effects have not been discussed in detail previously in the literature. This paper presents a study of the impacts of channel group delay distortion on high-speed backplane data transmissions. Equalization strategies for reducing the impact of group delay distortion are explored. A unique bit-edge equalization (BEE) scheme is presented that reduces the impact of channel group delay distortion by compressing the data spectrum in conjunction with optimizing the sampling phase. With transmitter (TX) pre-coding, the proposed BEE employs a 5-post-tap conventional symbol-spaced FIR (SSF) filter as the TX pre-emphasis, eliminates the need for a “delay and add” duobinary filter as in the conventional duobinary transceiver, and is more compatible with the bit-centre equalization (BCE) scheme. In this work, a typical Tyco 34-inch FR4 backplane channel is used as the comparison benchmark. A Matlab script based link simulation tool is used to evaluate the link performance. The optimality of the proposed BEE in reducing the impact of channel group delay distortion and mitigating ISI is demonstrated at a data rate as high as 12 Gbps.

The paper presents a case study of progressive collapse analysis of a selected multistory building. The subject of the numerical study is an existing 8-story steel framed structure built for fire tests in the Cardington Large Building Test Facility, UK. The problem is investigated using nonlinear dynamic finite element simulations carried out following the GSA guidelines. The paper focuses on model development for global models subject to increasing vertical loading and notional column removal. Taking advantage of parallel processing on multiprocessor computers, a detailed 3D model with large number of finite elements has been developed for the entire structure. The objective of the presented feasibility study is to identify modeling parameters affecting the final result (potential of progressive collapse) and propose a hierarchical verification and validation program for reducing outcome uncertainties.

An all-digital clock and data recovery (CDR) with a digital threshold decision updating technique for SFI-5 application is presented in this paper. The CDR updates its decision upon the phase error reaching a threshold value by examining the phase errors in the data bits within an examining window at the baud rate. High jitter tolerance performance is obtained and the phase acquisition can be achieved within one baud period. The proposed CDR is embodied with 900 transistors and the core CDR consumes 5 mW with 1.2 V supply at 2.5 Gb/s. Measured results verify the digital threshold decision technique and its low-complexity implementation for SFI-5 application.

A unique bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications is presented. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method aims to optimize the bit-edge amplitudes by equalizing only the edges of data bits with an adjustment of the sampling points where the error information is collected. This adjustment of sampling points in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the channel's far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs transmitter (TX) pre-coding in conjunction with TX pre-emphasis using a symbol-spaced FIR (SSF) filter. In this work, a detailed analytical comparison of the proposed BEE transceiver architecture with the conventional NRZ bit-centre equalization (BCE) and duobinary transceiver architectures is presented. The simulation results demonstrate that at 10+Gbps data rates, the proposed BEE is the most effective method for mitigating ISI in relatively high-loss channels.

This paper describes an assessment program for paratransit buses concerning their crashworthiness and safety of passengers. The program developed by the authors was approved by the Transit Office of the Florida Department of Transportation as a part of the Florida Vehicle Procurement Program (FVPP) in August 2007. Several valuable, worldwide vehicle safety standards were adopted in it with modifications addressing the bus construction process and relevance of particular structural components in crash events. Passenger compartment structure, which needs to be protected against the most dangerous accidents such as a side impact and a rollover, is a major area of concern in the standard. Lack of such standards may result in poor crashworthiness characteristics of the bus structure and in severe injuries and possible passenger fatalities. Either full-scale experiments or numerical standardized simulations were proposed as equivalent approval methods for paratransit buses. Selected results for partially validated Finite Element (FE) models and the nonlinear explicit dynamic code LS-DYNA were used to demonstrate a numerical approach for a bus structure approval. The FE models can also be used to assist the bus manufacturer in an effort to improve the crashworthiness of the new bus designs. The procedure described in this paper was implemented to monitor crashworthiness resistance of the paratransit buses distributed and operated in the state of Florida.

The type of twinning in sphalerite-type III–V compound semiconductors is well known. However, the detailed formation mechanism, although intensively studied in the last two decades, is not entirely understood. It is still widely accepted that twin formation is a rather fortuitous issue. In addition to many empirical observations and phenomenological explanations, there was a first theoretical approach by Hurle [Speculation Concerning the Causes of Twinning during Czochralski growth of Crystals having Diamond Cubic or Zinc-blende Structure, 1991], later refined. The theory predicts a correlation between crystal slope angle α and twin generation frequency, where α is defined as the angle between the tangent to the crystal surface and the growth axis. Angles of 70 . 53 ∘ and 74 . 21 ∘ should promote twinning, while that of 35 . 26 ∘ should reduce twin frequency. However, a critical review of experimental results on InP, grown by LEC (liquid encapsulated Czochralski) and VCz (vapor pressure controlled Czochralski) techniques, does not yield such a clear correlation. To shed some more light on the possible factors already discussed in literature, a systematic study based on statistical methods is performed. It can be shown that, at least for the Czochralski technique, twin formation is closely connected to the crystal growth rate and its fluctuations, i.e. instabilities of the growth system. This confirms some of the literature suggestions.

Several full-scale load tests were performed on a selected Florida highway bridge. The bridge was dynamically excited by two fully loaded trucks, and the strain, acceleration, and displacement at selected points were recorded for the investigation of the bridge’s dynamic response. Experimental data were compared with simplified vehicle and bridge finite-element models. The vehicle was represented as a three-dimensional mass–spring–damper system with 11 degrees of freedom, and the bridge was modeled as a combination of plate and beam elements that characterize the slab and girders, respectively. The equations of motion were formulated with physical components for the vehicle and modal components for the bridge. The coupled equations were solved using a central difference method. It was found that the numerical analysis matched well with the experimental data and was used to successfully explain critical dynamic phenomena observed during the testing. Impact factors for this tested bridge were thoroughly inv...

A comprehensive experimental material characterization and full-scale testing of structural connections of paratransit buses is presented in this paper. Structure-property relations were quantified for the constitutive material models used for finite element simulation-based crashworthiness research of paratransit buses. Several structural materials used by the paratransit bus industry were identified, and coupon size specimens were tested. A dynamic wall panel test with an impact hammer provided validation data for the finite element simulations. In addition, quasi-static laboratory tests of standard connections between the walls, floor, and the roof of a selected paratransit bus were performed. In addition to FE model validation, the connection testing allowed for thorough qualitative assessment of connection design, which resulted in improved crashworthy connection details. The experimental materials characterization and validation protocol described in this paper is consistent with the draft ...

This Paper demonstrates an attempt to link nonlinear (transient) oscillator behavior with phase noise. Phase noise generation is first studies, starting with examining Groszkowski's equation. After studying the mechanism, it is found that phase noise is determined by the transfer function and harmonics and based on which, a VCO design guideline is proposed to aid low phase noise VCO design. Then a novel VCO topology is proposed based on this guideline, aiming to reduce the harmonics and decrease the magnitude and the bandwidth of the transfer function. The circuit was designed and implemented in 0.13um IBM CMOS technology. The simulated performance at 2.4GHz was −133dBc/Hz at 1MHz offset with supply current of 3.07mA at 1V supply.

A delay-locked loop (DLL) based period synthesis is described. The proposed synthesizer architecture uses a single-loop DLL with phase interpolators to generate wide range of output frequencies. For the first time, the proposed period synthesis does overcome the integer-N limitation of the conventional DLL-based frequency multiplier, and achieve a small phase/frequency step. The delta-sigma modulation technique is applied at the phase selection stage to achieve a fine phase resolution. The spur performance in the frequency domain is also analyzed based on CMOS implementation. A system-level period synthesizer is built to verify the proposed architecture.

The paper presents an experimental study of the actual dynamic effects for a preselected typical highway bridge. Knowledge of the dynamic impact factors is important for accurate determination of the ultimate load capacity and performance assessment of constructed bridges. Static and dynamic field tests were performed on a two-lane concrete highway bridge built in 1999 on U.S. 90 in northwest Florida. During the tests, one or two fully loaded trucks crossed over the bridge, which was instrumented with strain gauges, accelerometers, and displacement transducers. A wooden plank was placed across the lanes for some runs to trigger extensive dynamic vibration and to simulate poor road surface conditions. Data collected from the tests were used for comprehensive assessment of the bridge under dynamic loading. Impact factors obtained from the tests with higher speeds were found larger than corresponding values recommended by bridge codes. Analysis revealed that stiff vehicle suspension, road surface imperfection, and "bouncing" of the truck loading contributed to the high impact factors. Experimental data were also used for validation of the finite-element models developed for the vehicle-bridge system.

This paper presents results of the finite element (FE) analysis of dynamic interaction between a heavy truck and a selected highway bridge on US 90 in Florida. FE analysis of vehicle-bridge interaction was conducted using commercial program LS-DYNA and the super computer at the Florida State University. Development and implementation of a detailed FE truck model with 3D suspension systems, pneumatic and rotating wheels, appropriate contact algorithms, allowed for realistic representation of the actual vehicle dynamic loading. Several static and dynamic field tests were performed on the same bridge. The experimental data was used for validation of the FE models of the bridge and the truck. Numerical results were found to match well with the experimental data. Results presented in the paper demonstrate a significant potential of using computational mechanics and LS-DYNA code for thorough investigation of the vehicle-bridge interaction, dynamic impact factors, and the ultimate loading of bridges.

Most of the bus safety standards in the USA are not applicable to cutaway buses for which a production process is split into two stages. First, the chassis and cab section are assembled by automobile manufactures. Then the vehicle is shipped to another company, where bus body and additional equipment are installed. Lack of strict structural standards for transit bus body builders stimulates the need for crashworthiness and safety evaluation for this category of vehicles. This study focused on a selected transit bus, the Ford Eldorado Aerotech 240. Due to the lack of design data the reverse engineering process was used to acquire the geometric data of the bus. The finite element (FE) model was developed based on the geometry obtained by disassembling and digitizing all major parts of the actual bus. The FE model consists of 73,600 finite elements, has 174 defined properties (groups of elements with the same features) and 23 material models. LS-DYNA non-linear, explicit, 3-D, dynamic FE computer code was used to simulate behavior of the FE model under different impact scenarios, such as front impact and side impact of two buses at various velocities.

This work presents a telemetric flight recorder which can be used in unmanned aerial vehicles. The device can store GPS position and altitude, measured with the use of pressure sensor HP03M, a flying platform. The most important subassembly of the recorder is an M2M family device H24 modem developed by Telit company. The modem interface communicates with the use of UART interface and AT commands. The autonomic work is provided by a microcontroller which is master component of the recorder. The ATmega 664P-AU from AVR family microcontrollers developed by Atmel is used. The functionality of the measurement system was developed in such a way that a GSM module can send current position to the base station on demand. In the paper the general description of the device and achieved results of tests are presented.

A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-/spl mu/m CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply.

CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-/spl mu/m CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with -83 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption.

The lock-in speed is an important performance criterion for ranking a frequency synthesizer, especially in wireless applications where the acquisition speed of the synthesizer determines how fast the communication can be switched from one channel to another or from off state to on. A novel fractional-N Phase Locked Loop (PLL) featuring fast acquisition and wide tuning range is proposed in this paper. The proposed method was verified in Simulink simulation.

A novel fractional-N Phase-Lock Loop (PLL) architecture is proposed in this paper. The architecture features a hybrid of DCO and VCO, which is controlled by a mixed-mode loop filter. The analog part of the filter works as the proportional path of the loop and the digital part as the integral path. The proposed architecture takes advantages of both analog PLL and All Digital PLL (ADPLL) and overcomes some problems encountered with each technique. The proposed solution has been verified in the behavioral level and a chip is under development.

The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.

The current mode digital-to-analog converter (iDAC) has been widely used in finite-impulse response (FIR) filter implementations as it is well-suited for high-speed operation. This paper proposes a novel solution to reduce the signal feed-through problem commonly encountered in current mode digital-to-analog converters in pre-emphasis circuits. To improve the eye opening, the circuit must be able to limit the flow of feed-through signal to the summing node. The proposed multi-tap pre-emphasis circuit has been simulated using an IBM 130nm CMOS technology.

A low supply voltage low phase noise 10-GHz CMOS quadrature LC-VCO (LC-QVCO) is systematically analyzed and designed for low power applications in wireline and wireless communication systems. Using a semi-empirical model, the impacts on VCO oscillation magnitude, loaded quality factor (Q loaded ), and oscillation frequency from the parasitic components of passive and active devices are formulated in simple mathematic equations. The predicted VCO performance and the widely used linear model of LC-QVCO are verified by timedomain simulations, frequency-domain total loop gain analysis, and measurement data based on a 120nm RF CMOS technology.

A pipeline Fast Fourier Transform (FFT) switch with built-in self-test is described. The pipeline FFT, a one-dimensional systolic array, is composed of complex butterflies and FFT switches. The FFT switches are cascadeable and can support the implementation of a radix-2 pipeline FFT of up to 8192 points. The 10 000 gate ASIC device is fabricated in 1.5μm HCMOS gate array technology, and supports a throughput of 25 Mwords s −1 .

An accurate feedback system analysis method is used as a tool for analyzing submicron CMOS LC-tank Quadrature VCOs. A simplified analysis for the closed-loop gain and oscillation frequency is developed, and good agreement is found between the feedback theorem and simulation results. The insight closed-loop gain is used to explore circuit design trade-offs.

This paper presents a 10-Gb/s backplane transmitter with a finite impulse response (FIR) pre-emphasis equalizer to suppress inter-symbol-interference (ISI) at data centers and transition edges simultaneously. The design concepts are discussed. Circuits in 0.13µm IBM CMOS technologies are given. Comparison with conventional data center oriented equalizer and transition edge oriented equalizer are carried out on a 40-inch FR4 differential backplane.

In this paper, we discuss an optimized current-mode logic (CML) circuit design technique for high-speed backplane transmission. The inductorless CML circuits are extensively used in high-speed digital circuits. With a given CMOS technology, the CML circuits can be optimally biased for higher speed operation with the considerations of speed, swing, power, load capacitance and area. Typical high-speed CML buffer and latch for 10-Gb/s transmission are designed with the optimized biasing technique with lower power consumption, and compact area (buffer: 10.2 times 14.4 mum2, latch: 30.4 times 32.8 mum2).

In this work, two unique decision feedback equalizers (DFE) for use in 10 Gb/s optical communications are presented. These equalizers are effective at cancelling post-cursor ISI as well as pre-cursor ISI without the use of a feed-forward equalizer (FFE). The removal of the FFE equalizer is desirable as it is very expensive from a chip real-estate perspective. The synthetic transmission lines used to achieve the analog delay in FFE filters also suffer from performance issues such as limited bandwidth, impedance mismatches, and nonlinearities which degrade the efficacy of the filter. The proposed filter structures will be evaluated via numerical simulation, and a comparison with standard FFE/DFE techniques will be made.

This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs in the high-speed circuits need to be considered, and either power or headroom may be traded for higher speed. The optimized biasing technique is thoroughly analyzed first in this paper, and a typical high-speed CML circuit is designed based on this technique.

This paper presents a novel transmitter structure serving as a bridge between high-speed serial data and low power ultra wideband (UWB) communication. A current mode logic (CML) based finite impulse response (FIR) structure is used to spectrally shape the data at the rate of 10 Gb/s with 5.36 pJ energy/bit consumption in CMOS 90 nm technology. Stacked inductors are used for wireless chip-to-chip transmission.

This paper presents a reconfigurable systolic array design suitable for multi-carrier wireless applications. The systolic array architecture includes coarse grained processing elements and interconnection switches. The systolic array can be configured as a Polyphase-FIR filter, DFT, Polyphase-DFT and IDFT-Polyphase function. A representative reconfigurable circuit has been designed and implemented on an FPGA for operation in the following modes: 32-point DFT; 8-channel Polyphase filter; 8-channel IDFT-Polyphase; and 8-channel Polyphase-DFT. Simulation results for the 32-point DFT circuit configuration show a performance of 240MOPS. Simulation results for the 8-channel Polyphase filter and 8-channel IDFT-Polyphase/Polyphase-DFT circuit configurations show that a throughput of 120 and 60MSPS respectively can be achieved. The circuit is scalable and can be extended to accommodate larger configurations and architectures. The scalability and reconfigurability of the circuitpsilas architecture provides a flexible solution for multi-carrier wireless applications incorporating Polyphase-DFT circuits.

In this paper, a low supply static 2:1 frequency divider based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The frequency divider uses a single 1.2-V supply voltage and consumes a total current of 32 mA. And the chip area is only 0.63 mm2 with bonding pads.

This paper presents a decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy channels. Forward equalization is not used in order to avoid noise enhancement. The sampling phase is optimized to achieve maximum signal-to-noise-ratio at the sampling instants. The coefficients of feedback finite-impulse-response filter and the gain of variable-gain-amplifier are obtained automatically by adaptive circuits. The vertical eye opening is almost doubled compared with a conventional decision-feedback-equalizer for a 56-inch channel with heavy loss more than -6.5 dB/GHz. The DFE is implemented in 0.13-mum IBM RF CMOS technologies. Results show an 8-tap DFE can open the highly blurred eye diagram, while a 12-tap conventional DFE can not open it. A 10-tap DFE yields a very clear eye diagram for PRBS-9 test patterns.

Low supply digital blocks for OC-768/STM-256 optical communication systems such as 1:2 demultiplexer (DEMUX), 2:1 multiplexer (MUX), 2:1 frequency divider and data decision circuit in 0.13 mum CMOS are presented. All proposed blocks are based on fully differential MOS current-mode logic (CML). Multi-stage output buffers are used to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split resistor (SR) loads are used to boost the bandwidth. High output resistance current sources are employed to achieve flat current source characteristic and allow the designed ICs to operate stably with wide process, voltage and temperature (PVT) variations. The main contribution of this work is that four proposed circuits can work at 40-Gb/s and beyond under a 1 V supply and consume low currents.

In recent years advancements in the field of wireless communications have generated interest in the deployment of multiple antenna systems (MIMO) for mobile terminals. Next generation wireless local area networks (WLANs) standards such as IEEE 8(12.1 In are based on MIMO and will be operating at bit rates above 200 Mbps. The physical layer (PHY) of the 802.11n supports multiple modulation schemes, multiple antennas configuration, variable code rate and multiple space-time coding schemes. Receiver architecture should be able to support all these features preferably in a single reconfigurable architecture. Besides all these requirements need to be designed and implemented under the strict low power and low complexity (low area) design criteria.

Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in high-speed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling at 5-Gb/s over 34" FR4 backplane, SPECTRE simulation in 0.18μm CMOS process has shown the design feasibility.

This paper presents the design of a high-speed wide-band frequency divider. The divider core is formed with a low voltage swing current mode logic (CML) structure, which enables high frequency operation at very low power dissipation. The divider exhibits very wide locking range from 4GHz - 41GHz, and it has an input sensitivity of -31dBm at 30GHz. The divider core draws only 750?A from a 1.2V supply. Post layout simulation results in 90-nm CMOS technology are provided.

This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization. This platform was created using MATLAB, qualified against Agilent's ADS SI suite, and correlated with measurements. This paper also describes the practical uses of such a simulator developed at Altera to predict link performance over backplanes.

An 8 Gb/s current mode logic (CML) transmitter with multi-tap FIR pre-emphasis has been implemented in 0.18 /spl mu/m CMOS technology and verified to operate with PRBS7 data over a 34 inch FR4 backplane. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. At the receive side, a frequency and phase-locked clock and data recovery (CDR) circuit incorporates a multiphase voltage-controlled oscillator (VCO) and a half-rate bang-bang phase/frequency detector (PFD) with embedded data retiming. The total power dissipation of the transceiver is 75 mW at a 1.8 V supply.

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18/spl mu/m CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50m W at a 1.8V supply.

Recent trends in the commercial use of fractional-N frequency synthesis can be attributed to the characteristic of independent loop bandwidth-channel spacing that results in low phase noise and relaxes the phase-locked loop (PLL) design constraints. This paper reviews several techniques used to implement fractional-N frequency synthesizers and discusses the advantages and disadvantages. It also addresses design options and associated trade-offs.

This paper presents a novel implementation technique using simple digital ASIC synthesis to generate a silicon layout of a multi-level PAM modulation circuit that incorporates a digitally adaptive pre-emphasis scheme. While computationally complex, the actual VLSI implementation is relatively simple, requires minimal power and generates a layout that minimizes the footprint. The results of the digital synthesis of several comparable adaptive circuits are detailed and compared. Several devices have been submitted for fabrication, via CMC, using the TSMC 0.18 /spl mu/m CMOS generic standard cell process.