A fast-lock PLL with over-tuning control

Authors :: Tadeusz Kwasniewski
Chao He
Source :: 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.
Publication Year :: 2012
Publisher :: IEEE, 2012.
Abstract: The lock-in speed is an important performance criterion for ranking a frequency synthesizer, especially in wireless applications where the acquisition speed of the synthesizer determines how fast the communication can be switched from one channel to another or from off state to on. A novel fractional-N Phase Locked Loop (PLL) featuring fast acquisition and wide tuning range is proposed in this paper. The proposed method was verified in Simulink simulation.

Subjects :: Phase-locked loop
Frequency synthesizer
Engineering
Record locking
Direct digital synthesizer
business.industry
Control (management)
Electronic engineering
Wireless
State (computer science)
business
Communication channel

Database :: OpenAIRE
Journal :: 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology
Accession number :: edsair.doi...........f57a0be75edf2f3a8170d235bed20ab2
Full Text :: https://doi.org/10.1109/icsict.2012.6466718

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