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This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A full parasitic capacitance model of diode-class ESD structures is presented in this paper, including not only the reversed-bias capacitance model in the circuit normal operation but the forward-bias capacitance model under the ESD stress. This model successfully calculates the ESD-induced capacitances which degrade the high-speed mix-signal and RF IC performances, and also deals with the puzzle why diode-class structures have a low discharge level with a small turn-on resistance. And a novel parameter CESDV, which is named as the parasitic capacitance unit kV ESD level for the ESD device, is also proposed. The experimental results imply that the MOS-bounded diode has a CESDV about 15fF/kV, far smaller than the normal diode about 30fF/kV. It is shown that the MOS-bounded diode is an appropriate choice for the high-speed mix-signal and RF ICs ESD protection.

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.

The paper presents a power analysis model for adiabatic SRAM. According to different performance frequency and different memory size, we simulate, analyze and compare adiabatic SRAM's power characteristics and propose the model. Based on the power analysis model, a scheme of array-division for adiabatic SRAM is presented. With array-division structure, the power dissipation is related to m, which is the array-division value. When the value increases, the main source of SRAM power is changed from word-line and cell-clock to decoder

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed

A novel method to adjust gain in CMOS infrared (IR) readout integrated circuit (ROIC) which is suitable for the application of small pixel size has been proposed in this paper. Current mirror is inserted in the pixel to adjust gain. Two comparators have been added outside of the pixel and provide the decision to select different gains. Adjustable gain makes the design of following signal process circuit easier and allows long integration time to increase SNR. With this method of automatic gain adjust, ROIC can deal with the current that varies from 40nA to 300nA, with the integration capacitor of 2pF and the integration time of 40/spl mu/s. An experimental 4/spl times/4-pixel ROIC has been designed and it will be fabricated with 0.5/spl mu/m DPDM n-well CMOS process.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 0.5/spl mu/m DPTM n-well CMOS process.

Design of CMOS high-speed self-regulating voltage-controlled oscillator (HSSR VCO) using negative skewed delay scheme is presented in this paper. With a SMIC standard logic 0.18-/spl mu/ 1.8V CMOS process, the simulation results show that the HSSR VCO can work at 2.2 GHz with good linearity in frequency-voltage space as over an acceptable tuning range as well as a built-in compensation for the delay variation caused by supply fluctuation.

An improved low power CMOS snapshot readout structure called OESCA (Odd-Even Snapshot Charge Amplifier) for focal plane array (FPA) is presented in this paper. Using two low power charge amplifiers as column readout circuit (one is for the odd-row readout and the other is for the even-row), this structure not only can eliminate the influence of column bus parasitic capacitance, but also can save 15% power dissipation of the column readout stage. The pixel circuit includes only three NMOSFETs. Thus, it is very suitable for large-format small-pixel lower-power readout circuit. An experimental 64/spl times/64 OESCA chip has been fabricated with 1.2-/spl mu/m Double-Poly Double-Metal (DPDM) n-well CMOS technology. The charge handling capacity is 10.37 pC with pixel size 50/spl times/50 /spl mu/m/sup 2/. A description of the readout circuit structure, pixel circuit, operation principle is given in detail. Both excellent simulation results and experimental results of the fabricated OESCA readout chip are presented.