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The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest to analog and RF designers. Various aspects of the model are discussed, such as Gummel symmetry, capacitance reciprocity at V DS = 0 V, parasitic resistances, junction modeling, distortion modeling, and noise modeling. Examples from circuit design are used to illustrate the benefits of the PSP model.

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

This paper reports recent progress in partially depleted (PD) SOI MOSFET modeling using a surface potential based approach. The new model is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including floating body simulation capability, parasitic body currents and capacitances. A nonlinear body resistance model is included for accurate characterization and simulation of body-contacted SOI devices. The PSP-SOI model has been verified using test data from 90 nm to 65 nm PD/SOI processes.

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which in their turn are obtained from the so-called Ward-Dutton charge partitioning scheme. For devices with a laterally nonuniform channel doping profile, however, it is shown in this paper that no terminal charges exist from which the capacitances can be derived. Instead, for such devices, a new model is presented for the capacitances themselves. Furthermore, a method is given to incorporate such a capacitance model into circuit simulators, which are traditionally based on terminal charge models. Comparison with two-dimensional device simulations and a segmentation model shows that for a constant mobility, the new capacitance model provides an accurate description for a MOSFET with a laterally diffused channel doping profile. Through a comparison with high-frequency measurements, the agreement between model and experimental results is discussed.

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

The increasing complexity of modern technologies has made semiconductor process and device development challenging. A reduction in the number of experimental tests and a detailed internal insight opens the way to a more optimized process in a shorter time at reduced costs and development time. This has largely increased the use of virtual technology platforms for technology development and circuit optimization in e.g. RF BiCMOS applications. The capability of accurate predictions and directly linking basic technology parameters to RF circuit performance makes virtual technology a very powerful tool during RF process and device development. Commercially available technology computer-aided design (TCAD) tools are generally used during device fabrication and characterization, process optimization, and circuit design. With three examples we illustrate the evolution of the virtual technology process used for RF BiCMOS development within NXP Semiconductors. In the first two examples, we illustrate device and process optimization while in the third example we describe a new way of combining device and process optimization with circuit simulations by means of a distributed equivalent circuit. It allows to take the interaction between the intrinsic device (i.e. device doping profile) and the parasitic environment (i.e. device architecture) efficiently into account for high-frequency applications and in particular for low-noise circuits.

In this work we study improvements of the high-frequency noise performance of HBT devices by means of layout and spacer optimization. Using an equivalent circuit, we identify the dominant noise sources and demonstrate that the reduction of the base-resistance induced thermal noise by means of dotted emitters in combination with lowering the edge contribution of the base-emitter capacitance (e.g. by emitter-base spacer optimization) translates into better noise performance.

This paper presents a general weak nonlinearity model that can be used to model, analyze and describe the distortion behavior of various low noise amplifier topologies in both narrowband and wideband applications. Represented by compact closed-form expressions our model can be easily utilized by both circuit designers and LNA design automation algorithms. Simulations for three LNA topologies at different operating conditions show that the model describes IM components with an error lower than 0.1% and a one order of magnitude faster response time. The model also indicates that for narrowband IM2@w1-w2 all the nonlinear capacitances can be neglected while for narrowband IM3 the nonlinear capacitances at the drainterminal can be neglected.

First the surface-potential-based compact MOS model, PSP, is introduced. After a discussion of the general advantages of this model, it is benchmarked against measurements from the 45 nm technology node. Finally, we zoom in on the modeling in PSP of two effects that are of special importance for RF applications: distortion and noise.

In this presentation we will focus on the two main sources of noise in CMOS devices which are of interest for RF circuit, design: flicker noise and thermal noise.

Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative "benchmark" tests that over the last two years were used to verify the physical behavior of the new model and its usefulness for future generations of CMOS IC design. These include newly developed tests and previously unavailable experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

The physical background of the thermal noise equations of the PSP MOSFET model [1] is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally.

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 micron CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

A large-signal non-quasi-static (NQS) model for RF CMOS circuit simulation is presented that can be built from channel segments described by conventional QS models like BSIM3 or MOS Model 9. This large-signal NQS model is shown to give a very accurate prediction of the high-frequency behaviour of the intrinsic transconductance, the power gain and input resistance.

Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators. >

This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18 /spl mu/m CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with principal component analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.

A prototype 0.5 /spl mu/m CMOS LNA with a noise figure of 2.2 dB and a gain of 16.9 dB at 900 MHz at a power consumption of 1.8 mW is reported. This result, and the noise figures obtained on 0.25 /spl mu/m CMOS, are reproduced by simulations, confirming that RF noise modeling can be accurately performed using our public domain MOS Model 9. Simulations are presented for similar LNAs realized in standard CMOS processes with gate dimensions down to 0.13 /spl mu/m. Provided high Q matching circuitry is used, for the latter gate length a noise figure of only 1.1 dB and 27 dB gain at 1800 MHz, at a minimal power consumption of only 0.2 mW, is predicted.

A new methodology for sensitivity analysis at circuit level in terms of process parameters is presented. Response functions for long-channel MOSFETs are found from process and device simulations. Responses for a device with arbitrary dimensions are subsequently calculated using the MOS MODEL 9 scaling rules.

A very fast, robust and accurate parameter extraction method for bipolar compact models has been developed. Using a combination of simplified expressions and selected measurements the iterative solution of the full model equations (e.g. using a circuit simulator) is avoided. The method is applied to the bipolar compact model MEXTRAM.

We demonstrate that by careful layout optimisation, particularly aimed at reducing the effective gate resistance, a record high maximum oscillation frequency fmax of 150 GHz can be obtained for an industrial 0.18 μm CMOS process showing a cut-off frequency fT of 70 GHz. A very low minimum noise figure and good suppression of the substrate noise using a guard-ring is also shown.

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

The thermal noise of short-channel NMOS transistors in a commercially available 0.13 -mm CMOS technology is studied. The experimental results are modelled with a non-quasi- static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parameters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In the optimised device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance. The ever-continuing downscaling of CMOS technologies has resulted in a strong improvement in the RF perfor- mance of MOS devices (1-3). Consequently, CMOS has become a viable option for analogue RF applications and RF system-on-chip. For the application of modern CMOS technologies in low-noise RF circuits, accurate modelling of noise is a prerequisite. In MOSFETs, there are two intrinsic sources of noise: 1/f noise and thermal noise, the latter being the topic of this paper. Thermal noise is due to the random thermal motion of charge carriers. It not only manifests itself in the drain current noise spectrum, but, due to the capacitive coupling between channel and gate, also in the gate current noise spectrum. The latter effect is known as 'induced gate noise'. In addition to the intrinsic MOSFET thermal noise, the parasitic resistances (gate resistance, bulk resistance, and source/drain resistances) also exhibit thermal noise. Thermal noise of deep-submicron MOSFETs has received considerable attention lately, triggered by publica- tions reporting a strong enhancement of thermal noise with respect to long-channel theory (4-8). In the earliest of these publications (4), thermal noise was found to be enhanced by a factor upto 12 in n-channel devices with gate length 0.7mm, and hot electrons were proposed to explain these results. More recently, Klein (5, 6) reported very similar enhancement of drain current thermal noise in devices with gate length 0.65mm and proposed a model that invokes heating of the charge carriers in the inversion channel to explain the experiments. For the induced gate noise, an even more dramatic enhancement factor as large as 30 was found by Knoblinger (7) for a 0.25 -mm gate length n-channel MOSFET. Evidently, these reported noise enhancements would seriously limit the viability of RF CMOS, and a detailed study is called for. In previous work (9-11), in sharpcontrast to the above- mentioned authors, only moderate enhancement of the MOSFET drain current thermal noise was found, mainly caused by parasitic resistances and channel length modula- tion. This was found for 0.35 -mm, 0.25 -mm, and 0.18 -mm CMOS technologies. MOSFET gate current thermal noise, on the other hand, was found to be enhanced more severely. This enhancement could be traced back to the effects of gate resistance, and the silicide-to-polysilicon contact resistance in particular. Although the thermal noise, as found in CMOS fabrication down to 0.18mm, seems fairly well understood, it remains important to study the phenomenon for more advanced CMOS technologies: it seems probable that at some point down the ITRS roadmap, the main assumption of our theory, i.e. thermal equilibrium, will break down. Therefore, in this work (which was reported earlier in (12)), we extend our study of MOSFET thermal noise to 0.13 -mm technology. We present a large number of new experimental results in the 1-18 GHz frequency range, and compare them with the predictions of our previously developed RF MOSFET model.

In this paper a new physical gate leakage model is introduced, which is both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF performance is studied.