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Your search keyword '"Clock stretching"' showing total 3 results
Start Over Descriptor "Clock stretching" Topic energy consumption
3 results on '"Clock stretching"'

1. Adaptive Energy-Efficient Variation-Aware Dynamic Frequency Management.

Author

Dorosti, H.

Subjects
INTERNET of things, AUTOMATION, INDUSTRIAL engineering, INDUSTRIES, ENERGY consumption
Abstract

Background and Objectives: Considering the fast growing low-power internet of things, the power/energy and performance constraints have become more challenging in design and operation time. Static and dynamic variations make the situation worse in terms of reliability, performance, and energy consumption. In this work, a novel slack measurement circuit is proposed to have precise frequency management based on timing violation measurement. Methods: the Proposed slack measurement circuit is based on measuring the delay difference between the edge clock pulse and possible transition on path end-points (primary outputs of design). The output of the proposed slack monitoring circuits is a digital code related to the current state of target critical path delay. In order to convert this digital code to equivalent delay difference, the delay of a reference gate is mandatory which is the basic unit in the proposed monitor. This monitor enables the design to have more precise and efficient frequency management, while maintaining the correct functionality regarding low-power mode. Results: Applying this method on a MIPS processor reduces the amount of performance penalty and recovery energy overhead up to 30% with only 2% additional hardware. Results for benchmark applications in low-power mode, show 7-30% power improvement in normal execution mode. If the application is resilient against occurred errors duo to timing violations, the proposed method achieves 20-60% power reduction considering approximate computation as long as application is showing resilience. The performance of the proposed method depends on the degree of application resilience against the timing errors. In order to keep generality of the proposed monitor for different applications, the resilience threshold is user programmable to configure according to the requirements of each application. Conclusion: The results show that precise frequency scheduling is more energy/power efficient in static and dynamic variation management. Utilizing a proper monitor capable of measuring the amount of violation will help to have finer frequency management. On the other hand, this method will help to use the resilience of application according to estimation about the possible error value based on measured violation amount. [ABSTRACT FROM AUTHOR]

Published
2022
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2. A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching.

Author

Chae, Kwanyeob and Mukhopadhyay, Saibal

Subjects
*PIPELINES, *ELECTRIC potential measurement, *PROTOTYPES, *ENERGY consumption, *ELECTRIC breakdown
Abstract

This paper presents a dynamic timing control technique to prevent timing errors in a pipeline under variations. Timing errors in a pipeline are prevented by borrowing time from the following stage and resolving the borrowed time by stretching the next clock cycle. This paper analyzes the operating principles of the proposed technique; presents the design of the required circuit components; and demonstrates its operation through fabrication and measurement of a prototype test-chip designed in an 180 nm CMOS process. The measurement results demonstrate that a system employing the dynamic timing control technique can operate in a wider frequency and voltage range. [ABSTRACT FROM AUTHOR]

Published
2014
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3. A robust ultra-low voltage CPU utilizing timing-error prevention

Author

Matti Sopanen, Arto Rantala, Jani Makipaa, Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Department of Micro and Nanosciences, TDK Nordic, Aalto-yliopisto, and Aalto University

Subjects
Engineering, Signoff, Ultra-low power (ULP), energy-efficiency, 02 engineering and technology, digital CMOS, Clock stretching, 7. Clean energy, near-threshold, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, SDG 7 - Affordable and Clean Energy, Electrical and Electronic Engineering, Variability, Digital CMOS, Digital electronics, ta113, Operating point, Energy-efficiency, ta213, business.industry, variability, 020208 electrical & electronic engineering, Near-threshold, lcsh:Applications of electric power, Energy consumption, timing-error prevention (TEP), lcsh:TK4001-4102, 020202 computer hardware & architecture, clock stretching, Timing-error prevention (TEP), Ultra-Low Power (ULP), CPU core voltage, business, Low voltage, Efficient energy use, Voltage
Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

Published
2015
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