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With the era of massive multi-core architecture targeting cloud computing for exascale high performance computing (HPC) and big data applications, large scale multi-core are made possible thanks to advanced 3D integration technologies. This paper presents an innovative concept of active silicon interposer with stacked chiplets, with the objective of maintaining overall power consumption budget, increasing chip to chip bandwidth, and preserving full system cost by smart system partitioning.

International audience; IoT node application requirements are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). This paper presents a versatile IoT node covering this gap in processing and energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. The AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with 207ns wake-up time optimized for short sporadic computing. OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) and crypto accelerators for more complex tasks. The node can perform up to 36GOPS while achieving 15,000x reduction from peak-to-idle power consumption. The interest of this versatile architecture is demonstrated with 105μW daily average power on an applicative classification scenario

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.

In order to face the inherent complexity of new radio access technologies and to address the development of multi-standard devices, an innovative reconfigurable baseband architecture based on a distributed control and communication framework is proposed. This architecture is tailored to the possibilities and limitations of next-generation CMOS nanotechnologies in terms of leakage and timing closure. A combination of technology features, message passing control model, network-on-chip, asynchronous implementation, clocking and power reduction policies is used. The 79.5 chip was manufactured in a 130 nm CMOS technology and is integrated in a prototyping platform to perform real-time experimentation of advanced MIMO OFDM based telecom techniques. It is composed of 23 functional units, such as computing intensive IPs, channel coding blocks, programmable DMA engines, an ARM946ES core, and an Ethernet interface. These elements are interconnected via an asynchronous layered network-on-chip using an interface that controls the communication and configuration parameters during application scheduling.

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.

High performance and high power efficiency are two mandatory constraints for multi-core systems in order to successfully handle the most recent applications in several fields, e.g. image processing and communication standards. Nowadays, hardware accelerators are often used along with several processing cores to achieve the desired performance while keeping high power efficiency. However, such systems impose an increased programming complexity due to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant overheads. This work presents a hardware mechanism in co-design with a standard programming interface (API) for embedded systems focusing to decrease overheads imposed by software implementation while increasing programmability and communication performance. The results show gains of up to 97% in latency and an increase of 40 times in throughput for synthetic traffics and an average decrease of 95% in communication time for an image processing application.

International audience; Thanks to their brain-like properties, neural networks outperform traditional algorithms in certain group of applications. However, since they are wire-dominated systems, their hardware implementation poses numerous challenges as high latency and energy consumption. The recent technological improvements allow for stacking few dies one on another and designing 3D electronic circuits. This creates opportunities for 3D efficient implementations of neural networks targeting high-performance applications. This work explores the gains of 3D technology for neural networks relying on neural cliques. A general study shows up to 55% reduction in terms of total interconnect length and interconnect power consumption, and 74% reduction of the maximal interconnect delay. The proposed approach is validated with a power management applicative test-case. We demonstrate that, in this scenario, the 3D architecture reduces interconnect length and power by 35% and the maximal delay by 57%, compared to 2D.

International audience; 3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.

With the era of massive multi-core architecture targeting cloud computing for high end performances or advanced consumer electronics with tighter power consumption constraints, 3D integration technology will allow to design large scale multi-core. Thanks to advanced available 3D technology, it will be possible to maintain overall power consumption budget, increase chip to chip bandwidth, and preserve overall system cost by smart system partitioning. One of the main challenge of such multi-cores is clearly the interconnect infrastructure. For designing such 3D multi-cores, it is required to address two primary concerns: the 3D physical link by itself, and advanced interconnects scaled to 3D. The paper present an overview of 3Dinterconnects with 3D asynchronous Network-on-Chip architectures, with focus on 3D asynchronous links, and advanced interconnect structures for memory caches in 3D.

In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended our works to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node. Furthermore, considering 32 nm deep submicron technologies, we demonstrated an Adaptive Voltage and Frequency architecture to compensate for in-die PVT variations. Area overhead and power reduction results are discussed all along the paper.

International audience; “Normally Off, Instantly On” applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible, and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power-gating techniques due to their long context-restoring phase. In this paper, we propose to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context. If the circuit is in the ‘ON’ state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, when context-saving functionality is included, for a typical application with only 1% of time spent in the ‘ON’ state, the energy gain exceeds 40%

FPGA have always taken benefit of the most advanced technology nodes for offering better performance than CPU and better time-to-market than ASSP. However, with the slow-down of technologies and its exponentially increasing cost, FPGA race towards better integration is nowadays compromised. One alternative path to scaling is to go 3D. This promising solution can offer scaling at a lower cost while solving some FPGA issues such as yield or I/Os management. However, 3D solutions come with some drawbacks with heterogeneous performances of 3D/2D links and limited 3D interconnections. In this paper, we show some recent advances on the usage of 3D technologies for enhancing FPGA capacities.

3D stacking has been viewed as a breakthrough solution for increasing performance in multi-core architectures. The hope is to solve some of the main issues in current multi-core architectures: external memory pressure and latency; I/O bottleneck; communication power consumption. In this paper, some advances of this field of research are shown, starting with a WIDEIO experience on a real chip for solving DRAM accesses issue. The integration of a 512 bit-width bus is demonstrated in a Network-on-Chip (NoC) multi-core framework and the resulting performance based on a 65nm prototype with 10μm diameter Through Silicon Vias (TSV). The potentiality of 3D scaling thanks to 3D asynchronous Network-on-Chip implementation is then shown. Finally, an innovative 3D stacked distributed cache strategy aimed at lowering memory latency and external memory bandwidth requirements is presented. This new memory partitioning demonstrates the efficiency of 3D stacking to rethink architectures for addressing multi-core scaling challenges.

As Systems-on-Chip size increase, the communication costs become critical and Networks-on-Chip (NoC) bring innovative solutions. Efficient stream-based protocols over NoC have been widely studied to address dataflow communications. They are usually controlled by a set of static parameters. However, new applications, such as high-resolution video decoders, present more data-dependent behaviors forcing communication protocols to support higher dynamicity. For this purpose, we present in this paper dynamic stream links for stream-based end-to-end NoC communications by introducing two link protocols, both independent of the transfer size, allowing to improve the hardware/software control flexibility. The proposed protocols have been modeled in a MPSoC virtual platform and the hardware cost evaluated. Based on simulations, we provide guidelines to exploit these protocols according to application needs.

International audience; —Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future " Power-on, Power-off " application adding Non-Volatility without significant burdening of the existing architectures.

P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multibanked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm2 with 2W power consumption (worst-case). P2012 can run standard OpenCLTM and proprietary Native Programming Model SW components to achieve the highest level of control on applicationto- resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs.

3D stacking is seen as one of the most interesting technologies for System-on-Chip (SoC) developments. However, 3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range of products. In this paper, we are investigating 3D Network-on-Chip has a promising solution for increased modularity and scalability. We show that an efficient implementation based on asynchronous logic provides an available bandwidth of 64GB/s for only 700 TSV, outperforming classical interfaces while simplifying the assembly process. We also point out the benefit in terms of power consumption for these new interfaces with a gain of 5 times compared to classical LPDDR2 interfaces.

New memories, such as non-volatile resistive memories present bright prospect in catering to the ever-growing memory needs. In this paper, we investigate the usage of Oxide Resistive Random Access Memory (OxRRAM) to improve the communication switchboxes of Field-Programmable-Gate-Arrays (FPGAs). We prove the interest of using unipolar OxRRAM in such devices thanks to a complete methodology, starting from compact model based on self-consistent physical model up to architectural evaluation using typical FPGA benchmarks. Besides, the architectural gains in terms of area by 1.4x and write time by 17.4x in comparison with phase-change memories (PCM). An improvement in area by 4.82x and write time by 285.7x for conventional Flash technology as well as a reduction in overall delay by 49.3% due to the reduced on-resistance and smaller size are reported.

The MAGALI chip is a 65nm digital baseband dedicated to advanced telecommunication applications. Based on a 15-router mesh Network-on-Chip - NoC, it embeds 22 Processing Elements - PE performing the different functions of a complex baseband in a programmable manner. The NoC framework is based on asynchronous routers which provide a complete Globally Asynchronous Locally Synchronous -- GALS framework. Thanks to this structure, each PE is a synchronous island with a programmable frequency. On the architectural side, the NoC supports fast reconfiguration thanks to a distributed scheme. In this demonstration, we propose to show the reconfiguration capabilities of the MAGALI chip on three modes of a 3GPP-LTE receiver part, by switching on-the-fly between these three modes. The resulting transmission quality with different levels of upcoming signal noises is shown.

New generation of telecommunication applications requires highly efficient processing units to tackle with the increasing signal processing algorithmic complexity. They also need to be flexible for handling a large range of radio access technology with specifications moving very fast. As devices including telecommunication features are, per nature, mobile, the high level of flexibility must be achieved while preserving very low power consumption. In this paper, a high performance low-power application-specific processor is proposed for complex signal processing. Thanks to dedicated control architecture, this processor exhibits an average 81% utilization rate of its principal operator, a complex MAC for a 3GPP-LTE application. The main innovations are the use of a reconfigurable profile and instruction cache strategy to reduce power consumption. This leads to a 10× reduction of the control power consumption. As a result, an average 50 mW power consumption is measured after implementation in a low-power 65 nm technology while delivering 3.2 GOPS. Finally, a comparison with state-of-the-art low-power DSP shows at least 24 % gain.

3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range products. In this paper, we investigate three promising perspectives for short to medium terms adoption of such technology in high-end System-on-Chip built around multi-core architectures: the wide bus concept will help solving high bandwidth requirements with external memory. 3D Network-on-Chip is a promising solution for increased modularity and scalability. We show that an efficient implementation provides an available bandwidth outperforming classical interfaces. Finally, we put in perspective the active interposer concept which aims at simplifying and improving power, test and debug management.

While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This paper aims to present an overview of new, far-reaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.

MPSoC architectures bring flexibility and performance, but to avoid high power consumption, they still require a careful design. When taking into account variability in advanced CMOS technologies, individual optimization of each chip is necessary. In this paper, we present an approach based on Game Theory to address this issue at run-time in a distributed way, frequencies are dynamically adjusted according to changes in the system, so that power consumption is reduced while application constraints are fulfilled. Software and hardware solutions are proposed for different flexibility/performance trade-offs. Results show a latency of 5ms and an area of 0.014m² for the optimization stage in the hardware implementation. These figures are promising and allow envisaging run-time optimization on large-scale multi-cores.

Emerging non-volatile resistive memories such as Phase Change Memories (PCMs) are promising candidates to replace Flash and SRAM memories in some applications. This paper introduces a novel memory node for Field-Programmable Gate Arrays (FPGAs). We propose an elementary circuit storing the reconfiguration signals by means of two resistive memories and one programming transistor. The area and write time of the proposed node are investigated and their impact on complex circuits is assessed. We show that the elementary memory node yields an improvement in area and write time of 3.4× and 16× respectively vs. a regular Flash implementation. We use the designed memory node to reconfigure the switchbox in the routing part of FPGAs, and we demonstrate a delay reduction up to 50% on a benchmark of logic circuits that we mapped on an FPGA architecture thanks to the area saving and especially to the low on-resistance of PCMs.

The back-gate terminal on double-gate ambipolar transistors can be used as a powerful vector to achieve fine-grain logic reconfigurability. This paper describes ways of exploiting this property to improve on standard cell logic techniques, and to build logic gates with tunable functionalities. Given the vastly reduced transistor count, conventional use of reconfigurable interconnect at the cell level would lead to large overhead, and new interconnect strategies are required. We explore two types of interconnect architectures (island-style and cell-matrix) and develop a mapping method to evaluate trade-offs between matrix occupation, cluster size and switch requirements.

The complexity of MP2SoC architectures to come is such that many issues arise simultaneously, such as multicore programming, system performance, reliability, scalability, etc. The key to solve these issues is self-adaptability: the chips to come have to integrate the required software and hardware means to monitor and self-react to the various kinds of events that are likely to occur during chip's lifetime. The paper describes the design principles of a software based approach used to monitor manycore architectures running multi-threaded functional applications. The approach takes advantage of an in-memory database (as well as appropriate means to store, handle, and retrieve accumulated monitoring data) to achieve the monitoring task as simply as possible. After a presentation of the distributed database (called DRET), a case study is presented, along with performance results that clearly show the interest of the approach.

Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.

Baseband processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocol (e.g. 63 for 3GPP-LTE), the number of protocols to be supported by a single chip (≫10 in 2010) and new applications requiring a handover between protocols. The second concern is related to performance and power consumption: performance demands are exploding (up to 100GOPS are now required) with decreasing power consumption constraints (roughly 500mW).

Overall complexity of regular architectures is drastically increasing in nowadays System-on-Chip (SoC). Many cores are embedded in the same device and interconnected with a Network-on-Chip (NoC), providing more functionality with higher performance. The complexity of such systems introduces many challenges; one of them, probably the most important, is the power management. This paper focuses on the use of low-cost optimization mechanisms able to manage at run-time the SoC power consumption, when sequentially running applications with very different performance features, on chips with unequal characteristics due to technology variability. The optimization process is used to set the appropriate frequency of cores each time the application changes. This process has to meet some constraints. First of all, it operates intrusively on the fly to tackle changes in the system. Besides, fast response, low complexity and stability are required to have an efficient and reliable control scheme. The complexity of the optimization process has to scale with the number of cores. As a consequence, centralized optimization methods may present some drawbacks when the number of cores goes up to hundred. On the other side, distributed optimization methods can scale better, but may increase the total communications in the system. In this paper, we propose a distributed technique inspired by Game Theory (GT) to solve this optimization issue. In order to show the pertinence of the approach, we compare this solution to a centralized one based on state-of-the-art Lagrangian method. A telecom test-case application is used to compute the efficiency of the both techniques. Hardware/Software implementations of the game theoretic approach are proposed. We show that the optimization stage has an average latency of 5 ms and an area of 0.014 mm2 in 65 nm technology for the hardware implementation, which is really encouraging when considering SoC constraints.

In the context of heterogeneous NoC architectures for embedded systems, it is today mandatory to support multiple applications given the plurality of standards and usages. While static reconfiguration between applications has already been extensively studied, we propose a potential increase in hardware resource usage by enabling concurrent or overlapping applications on the top of a heterogeneous NoC platform. In this paper, we describe a distributed sequencing protocol allowing hardware resource sharing between several applications. This protocol ensures correct synchronization of the processing between hardware resources without the need of a global fine-grain scheduler on the system, thus alleviating the pressure on the run-time system. The proposed protocol has been integrated and validated in a NoC-based digital baseband for 4G SDR telecom applications, and was integrated on a manufactured chip on a STMicroelectronics CMOS 65nm LP technology.

The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on- Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.

High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6Gbps @385MHz, with an average 38mW power consumption.

In this paper we propose an adaptive technique to reduce power consumption of Multiprocessor Systems-on-Chip. The method, based on Game Theory, optimizes the frequencies of local processors while fulfilling applicative real-time constraints. Contrary to other approaches, our solution is compatible with reconfigurable Systems-on-Chip. The obtained power consumption gains on a telecommunication test-case are between 10% and 25%, while the reaction time to temporal variations due to application reconfiguration is less than 25μs.

Advanced telecommunication applications require more and more flexibility. Static and run-time configuration mechanisms, as well as plug-in computing units are two solutions to solve this issue. In this paper, we propose an open architec- ture, dedicated to complex data-flow applications, fulfilling these requirements thanks to a distributed configuration scheme and a standard interface for data flow computing units. Based on this architecture, an open platform demonstrator has been designed. Simulation results on a 3GPP/LTE application are presented, showing a reconfiguration time overhead of only 2.6%.

While Network-on-Chip aspects such as topologies, routing strategies or Quality-of-Service have been largely studied, the mapping of real applications on distributed NoC-based architecture is still an open issue. In this paper, we address this issue for complex reconfigurable data-flow applications. We introduce the concept of Communication and Configuration Controller (CCC) which interacts both with the usual Network Interface and the IP core structure. The proposed CCC is a programmable template-based architecture, which provides solutions to manage reconfiguration flows, data synchronizations and global control signaling. An implementation of the CCC is presented, and its performances in a 65nm technology are discussed through a concrete telecommunication application.

International audience; A Cognitive Radio is the final point of software-defined radio platform evolution: a fully reconfigurable radio that changes its communication modules depending on network and/or user demands. His definition on reconfigurability is very broad and we only focus on the heterogeneous reconfigurable hardware platform for Cognitive Radio. Software Defined Radio (SDR) basically refers to a set of techniques that permit the reconfiguration of a communication system without the need to change any hardware system element. The goal of Software Defined Radio is to produce communication devices which can support several different services. These terminals must adapt their hardware structure in function of the wireless networks such as GSM, UMTS, wireless LAN standards like IEEE 802.11a/b/g... As a consequence, NoC offer good perspectives to future SoC in the way to satisfy SDR concept. Conception, validation and evaluation of solutions for NoC design (mapping of cores, topology, FIFO and link sizes) is conducted through simulations. We are proposing to extend the NoC structure to a FPGA where PR (Partial Reconfiguration) is used to dynamically reconfigure the requested IP block of the telecommunication chain. This work is part of our contribution for E2RII project and IDROMEL project.

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units within a GALS NOC. network-on-chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for DVFS mechanisms. GALS NoC provides scalable communications and a natural split between timing domains. The proposed low power architecture is based on the association of a local clock generator and a local power control mixing VDD-hopping and super cut-off techniques. No fine control software is required during voltage and frequency scaling. A minimal latency cost is observed together with an efficient local power control.

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.

International audience; This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption.

In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. For power reduction, voltage and frequency scaling techniques have been applied successfully to CPUs but never with a generic approach for all IPs within a SoC. Network-on-Chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for easy IP unit integration. GALS NoC provides scalable communications and a clear split between timing domains. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units integration within a GALS NOC. The proposed DVFS architecture is based on the association of local clock generator and VDD-hopping between two given voltages. No fine control software is required during any voltage and frequency re-programming. As a result, minimal latency cost is observed. The power efficiency of the proposed system has been evaluated close to 95%.

The FAUST chip integrates a baseband processing architecture in which communications between IPs are supported by an asynchronous network-on-chip (NoC). This distributed and modular structure facilitates physical implementation and power management. A 20-node NoC is implemented in 79.5mm2 using 0.13mum 6M CMOS to address 100Mb/s telecom systems

The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.

International audience; The trend nowadays is to integrate telecommunication system on complex SoC. But the requirements of such architecture in terms of interconnection and bandwidth constraints lead designers to propose innovative solutions such as networks-on-chip (NoC). In this paper we address a NoC-based implementation for a 4G modem. We propose a modelling environment based on a network simulation tool to evaluate its performance and set critical parameters. We present results validating our transceiver modem and showing the pertinence of the study for design exploration compared to other approaches.