Search

Device simulations of laser induced SEU in an SRAM cell are performed with pulse durations from 100 fs to 100 [micro]s. SEU threshold energy is notably dependent on the pulse duration. Two regimes are identified and modeled analytically and electrically. Index Terms--Critical charge, device simulation, laser testing, pulse duration, single event upset.

Abstract: Failure analysis techniques had been proved to be efficient to localize defects allowing root cause analysis and corrective actions at design or manufacturing level. Unfortunately, end user’s component expertise laboratories have very rarely access to the device design (CAD) they are analysing and characterizing. Electronics components come like a black box so they have to find out the information by other means to be able to link an abnormal electronic behaviour to a specific internal structure. We have proven that Laser Stimulation (LS) is a valuable technique to overcome this issue. These techniques allow a very good correlation regarding the sensitive sites on the device and the electrical functions performed. We have embedded these techniques in a specific test flow to perform CADless accurate device failure analysis and characterization of margin evolutions in operating parameters for reliability study purposes. [Copyright &y& Elsevier]

Abstract: A large range of commercial deep submicron VLSI devices are used for avionic designs. Due to the scaling down, an ever higher level of integration and the use of new materials in foundries, the main failure mechanisms are changing while new ones appear. Lifetimes related to these failure mechanisms are suspected of being shorter and shorter so failure rate prediction becomes a great challenge for deep submicron (DSM) semiconductor reliability. We propose in this paper, a new approach based on technologies analysis in order to determine potential reliability risks regarding the specific use of DSM components for avionic applications. [Copyright &y& Elsevier]

Abstract: We present in this study the effect of electrical ageing on silicon (Si) NPN bipolar transistors. This study is based on a sample of half-hundred components, which have been fabricated in the early 1980s, which represents an exceptional experience feedback. By means of static and low frequency noise measurements, which are used as diagnostic tools for reliability assessment, we have noticed a good accordance with a physical model based on an oxide charge modulation. We have also used emission microscopy and electron beam-induced current analysis in order to visualize and to localize the defects in the structure. These have been located in the spacer oxide at the periphery of the base-emitter junction. [Copyright &y& Elsevier]

Abstract: Various optical defect localization techniques are applied on the same integrated circuits (IC). These circuits were previously stressed by Electro Static Discharges (ESD) to create defects. The results obtained by each technique were analyzed to determine the nature of the defects. The different data are compared to assess their sensitivity and to evaluate the contribution of each technique in a failure analysis flow. [Copyright &y& Elsevier]