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This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60[degrees]. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-[micro]m CMOS process, our circuit takes 30[micro]s to reject the frequency offset of +200 kHz within the accuracy of [+ or -] 5 ppm, with 60-DFFs for a time-to-digital converter. Index Terms--Frequency offset, frequency synthesizer, low intermediate frequency, stability, time-to-digital converter (TDC).

Design and modeling of a micromachined high-Q tunable capacitor with large tuning range and a vertical planar spiral inductor, implemented in a microelectromechanical system, is described and discussed.

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-/[micro]m CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%. Index Terms--Adder, dynamic logic, low-power, skewed logic.

The results of two techniques for optical carrier regeneration and wavelength reuse using semiconductor optical amplifiers (SOAs) are presented in this paper. The main objective is to recover an optical carrier by erasing its amplitude modulation. The first technique employs gain compression of deeply saturated SOAs. The second technique uses a feed-forward approach, where a delayed current signal is injected into the SOA with the same shape of the incoming optical pulse. The second technique could be capable to recover the optical carrier with less than 3-dB noise. However, it was observed that the SOA gain recovery time limits the maximum usable bit rate. Theoretical simulation showed good agreement with experimental results. Index Terms--Optical carrier regeneration, optical pulse reshaping, optical wavelength reuse, semiconductor optical amplifier.

We present a computationally efficient method to stimulate lossy transmission lines using iterative linear least square fitting (ILLSF) model synthesis and piecewise recursive convolution (PRC). Based on the generalized method of characteristics, transmission lines are modeled with characteristic impedances and waveform generators. Thus the first major task involves network synthesis. The second is efficient computation of the synthesized waveform generators which requires computationally expensive convolution integral evaluation during transient simulation of transmission lines. The superior performance of ILLSF and the efficiency of PRC will be demonstrated for the transient simulation of coupled lossy transmission lines.

A transformer filter is fabricated with three piezoelectric ceramic disk transducers and two sheets of thin insulator. Its equivalent circuit is derived from the Mason's model of a thickness-driven piezoelectric transducer. The electric input near its fundamental resonance frequency is applied to the center transducer and the output voltages across the left and right transducers are connected in parallel or in series to the resistor load. The load characteristics at resonance frequencies under various resistor loads and the frequency characteristics near the resonance frequency under no load have been investigated. Moreover, symbolic expressions for input impedances, voltage ratios, resonance frequencies, phase angles between the input and output voltages, and bandwidths have been derived. The values calculated from those symbolic expressions are shown to agree well with the measurement values.

The capacitative characteristics of metal oxide semiconductor field effect transistor (MOSFET) are modelled by a new technique to determine the accurate simulation of deep submicrometer integrated circuits. This model describes the short channel effects of the deep micrometer MOSFETs. The description is obtained from the analysis of series resistance effects and velocity saturation.

A nonlinear mixed 2D-1D thermal insulator, iTSIM, was used to study the power-to-failure relationship used to determine the electrical overstress (EOS) failure thresholds of integrated circuits. The EOS performance was enhanced when the power density decreased and heat source size increased. EOS and electrostatic discharge are detrimental to the reliability of integrated circuits.

We introduce a new concept called moment components and a new method based on it to obtain passive reduced-order models of interconnect networks. In this method, the impedance matrix moments of the interconnect network are partitioned into their inductive, capacitive and mixed inductive/capacitive moment components. The method of moment components is described in a formal manner using analysis and synthesis equalities. Two significant contributions of the method of moment components are: 1) new decomposition of moments into parts which reflect passivity in all moments of passive networks and 2) the analysis equalities impart a regular pattern in terms of the moment components, thus simplifying the moment generation for our method. None of these features is observable in conventional complete moment terms. Two new methods for obtaining passive reduced-order models based on the method of moment components are introduced. The passive reduced-order models are obtained by matching their impedance moment components to those of the original interconnect network through the synthesis equalities. Due to nonnegative definiteness of the moment components, the match in the moment components preserves the passivity of the original interconnect in the reduced-order model. The method of moment components does not have the instability problem of general moment matching techniques. The reduced-order model is specifically targeted for fast timing simulators so that interconnect effects can be simulated efficiently. Consequently, the calculation of all model parameters is based on explicitly formulated analytical expressions. To maintain the speed advantage of the fast timing simulator, the number of moments needs to be kept low. However, since the capacitive and inductive moment components of the original interconnect are matched respectively to the capacitive and inductive moment components of the reduced-order model, a more refined match is achieved and accurate results are obtained even with a small number of moments. Simulation results of original interconnect networks and their reduced-order models are compared using circuits of practical interest. Index Terms--Interconnect timing simulation, moment components, moment matching, passive-model order reduction.

This paper presents a new technique to simulate RLC/RC interconnects and driving nonlinear circuits with high computational efficiency. We introduce ILLIADS-I, a fast transistor-level timing simulator for MOS circuits driving RLC/RC interconnects. The RLC/RC interconnect networks are reduced to an appropriate model and then simulated in the timing simulator as a modified generic circuit primitive. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. Index Terms - General load circuit, generic circuit primitive, interconnect timing simulation, moment matching.