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A comprehensive analysis of the impact of the finite gain-bandwidth product (GBW) in amplifiers and the excess loop delay on a parallel inultibit CT AE ADC for an orthogonal frequency division multiplexing OFDM ultra-wideband (UWB) receiver has been carried out in this paper. The overall converter consists of two CT AS modulators covering two sub-bands (each of them implemented by a third and a fourth order CT AE modulator) that are arranged to operate in parallel. Our study was based on the dependence of the noise transfer function (NTF) poles and zeroes locus in the z-plane on these two nonideal effects for both modulators from a theoretical approach. The corresponding STFs were also analytically evaluated. System-level simulations have been accomplished too. Amplifiers were modeled according to a single-pole transfer function. Using the modified Z-transform method the dependence of the NTF poles and zeroes locus in the z-plane on the finite GBW and on excess loop delay was obtained when the DAC pulse end occurs in the current ("early") or in the following ("late") clock cycle. NTF poles and zeroes loci were evaluated as a function of the two nonideal effects considered sepa-rately or combined. [ABSTRACT FROM AUTHOR]

In this article a current-mode, second-order, CT Sigma-Delta modulator operating at a sampling frequency of 25 MHz and with an oversampling ratio of 64 has been designed. The modulator consists of current-mode, differential integrators based on a single-stage folded cascode topology and switched capacitors DACs cells generating exponential feedback waveforms. The modulator was analysed in detail from both a system- and a circuit-level point of view. A 'short' exponential DAC pulse, namely, an exponential pulse whose time constant is lower than the pulse width, was used to improve jitter rejection. Modulator feedback coefficients were analytically derived for an exponential feedback waveform. Jitter considerations paying special attention to its impact on CT Sigma-Delta modulators were presented, and two different contributions distinguished: independent jitter and accumulated jitter. Finally, functional- and transistor-level simulations have been accomplished to obtain significant features of the modulator performance. [ABSTRACT FROM AUTHOR]

Abstract: A comprehensive study of the impact of the finite gain-bandwidth product (GBW) in amplifiers and the excess loop delay on CT modulators has been carried out in this paper. Variations in the modulator coefficients have been included too. Considering a second order modulator, our study was based on the dependence of the NTF poles and zeroes locus in the z-plane on these two non-ideal effects from both an analytical and a computer simulation approach. The corresponding STFs were also analytically evaluated. The theoretical and the simulated results have been compared with the experimental results obtained from a test-chip recently designed and implemented. Amplifiers were modeled according to a single-pole transfer function. Using the modified Z-transform method the dependence of the NTF poles and zeroes locus in the z-plane on the finite GBW and on excess loop delay was obtained when the DAC pulse end occurs in the current (“early”) or in the following (“late”) clock cycle. Once the theoretical analysis was validated, NTF poles and zeroes loci were evaluated as a function of the two non-ideal effects considered separately or combined. In each case, the order of the modulator loop filter was discussed. The finite GBW effect can be compensated including an intentional “early” DAC pulse. This pulse can be implemented in the modulator by changing the sampling instant in the embedded ADC with respect to the instant DACs are enabled by using a simple delay circuit for the ADC clock. Thus, the modulator power consumption can be significantly reduced. [Copyright &y& Elsevier]

Abstract: In this work the design of a continuous-time modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5MHz and 8, resulting in a clock frequency of 1GHz. It was designed and implemented in a standard 90nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8mW from a nominal power supply of 1V. [Copyright &y& Elsevier]