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This article reviews current research and development as well as future opportunities for packaging and antenna integration technologies for silicon-based millimeter-wave phased arrays in emerging communication applications. Implementations of state-of-the-art silicon-based phased arrays below 100 GHz are discussed, with emphasis on array architectures for scaling, antenna integration options, substrate materials and process, antenna design, and IC-package codesign. Opportunities and challenges to support phased array applications beyond 100 GHz are then presented, including emerging packaging architectures, interconnect characterization requirements, thermal management approaches, heterogeneous integration of multifunction chiplets, and novel antenna technologies.

As antenna element size and pitch are in the order of millimeters, i.e. comparable to wavelength at millimeter‐wave (mmWave) frequencies, antenna‐in‐package (AiP) solutions are more feasible for design and manufacturing than at other frequencies. This chapter first discusses the needs and challenges of performing electrical, mechanical, and thermal co‐design for AiP modules with a particular focus on mmWave front‐end module implementation in 28‐GHz high‐speed wireless data transmission applications. Furthermore, it reviews the thermal management considerations for next‐generation heterogeneous integrated systems that are also applicable to phased array front‐end modules. Different cooling methodologies are discussed for future communication devices under various power dissipation conditions. During the design iterations, simulation and measurement of key aspects such as antenna performance (bandwidth, gain, radiation patterns), cooling solutions, and warpage conditions need to be evaluated and optimized to ensure that performance meets the overall system specifications.

The increasing capabilities of high‐speed silicon technologies have made millimeter‐wave frequencies attractive for low‐cost applications. This chapter focuses on large‐array antenna‐in‐package (AiP) designs based on surface laminar circuit (SLC) technology at 28 and 94 GHz. It investigates antenna designs considering both manufacturability and the general performance requirements and presents a 30.5‐GHz antenna design and associated characterization results. The antenna design is based on SLC technology and supports both horizontal and vertical polarizations to enable realization of a large phased‐array module with multiple simultaneous beams for 5G applications. The chapter provides information on the AiP portion of the first reported SiGe‐based scalable phased‐array module to illustrate the challenges and initial solutions. Millimeter‐wave scaled phased arrays support many antenna elements. Phased‐array scaling is advantageous because it provides a path for supporting antenna arrays with a larger number of elements than a single integrated circuit can support.

Silicon-based millimeter-wave (mm-wave) phased-array technologies are enabling directional wireless data communications at Gb/s speeds. In this paper, we review and discuss the challenges of implementing a multichip phased-array antenna module for mm-wave applications using organic buildup substrate technology. A prototype test vehicle has been fabricated and studied to evaluate the antenna and interconnect performance, dielectric properties, package substrate warpage conditions at different temperatures, chip- and board-level joint process reliability, and thermal management feasibility for cooling. Based on the learning from the test vehicle, an organic-based multilayered phased-array antenna package for 28-GHz mm-wave radio access applications is implemented. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct probing measurements on a single-antenna element of the package show over 3 GHz of bandwidth and 3-dBi gain at 28 GHz. A phased-array transceiver module has been developed with the package; the module includes four SiGe BiCMOS ICs attached using flip-chip assembly. Module-level measurements in the TX mode show a 35-dB near-ideal output power increase for 64-element power combining; 64-element radiation pattern measurements are reported with a steering range of ± 50° without tapering in off-boresight directions, and 64-element radiation pattern measurements with tapering show achievement of a sidelobe level lower than −20 dB. The transceiver modules achieved 20.64-Gb/s throughput with 256 QAM and 800-MHz bandwidth in direct over-the-air link measurement results.

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (

We report on efforts to develop a high speed, low cost, low energy chip scale optical module for co-packaging on a first-level organic substrate for HPC and Data Center applications.

To address the abating performance improvements from device scaling, innovative 2.5-D and 3-D integrated circuits with vertical interconnects called through-silicon vias (TSVs) have been widely explored. This paper reviews TSVs with focus on the following: 1) key drivers for TSV-based integration; 2) TSV fabrication techniques; 3) TSV electrical and thermomechanical performance fundamentals and characterization techniques; and 4) novel technologies to attain enhanced performance beyond the state-of-the-art TSVs.

This paper motivates the need for scaled phased arrays and outlines key challenges for their implementation. Design trade-offs are discussed for important aspects such as beamforming architecture, module-level realization with antennas and packaging, and digital control. Two recently introduced scaled 64-element dual polarized phased array designs are reviewed as implementation examples. (1) A phased array transceiver module operating at 28-GHz supporting 5G applications, and (2) TX and RX phased arrays operating at 94-GHz suitable for backhaul and imaging applications. An outlook for future opportunities with phased array scaling is provided.

Co-design and integration of RFIC, package, and antennas are critical to enable 5G wireless communications and is particularly challenging at mmWave frequencies. This paper reviews two different aspects of mmWave antenna module packaging and integration for base station and user equipment applications, respectively. We first present the challenges, implementation, and characterization of a 28­GHz phased-array module with 64 dual polarized antennas for 5G base station applications. Next, we describe a compact, low-power, 60-GHz switched-beam transceiver module suitable for handset integration incorporating 4 antennas that supports both normal and end-fire directions for a wide link spatial coverage.

Directional communication at millimeter-wave (mmWave) frequencies is one of the key technologies under development towards the anticipated deployment of fifth generation mobile access (5G). Silicon-based multi-antenna systems are strong candidates for the implementation of such directional links; however, the performance requirements are in general significantly more challenging than those posed by mmWave WLAN links demonstrated so far (e.g. for 802.11ad). This work presents an overview of recent innovations in circuit design, antenna design, and beamforming architecture which enable complex phased arrays with precise and agile beamforming for mmWave-based 5G communications. Specifically, this work discusses: (1) a 28-GHz phase shifting transceiver front end, (2) beamforming architecture considerations to enable dual polarized operation as well as multi beam configurability, and (3) two different 28-GHz antenna-in-package (AiP) designs. These advances have been jointly demonstrated in a 64-element dual polarized phased array antenna module (PAAM) consisting of four SiGe ICs and an AiP array. The PAAM supports two simultaneous and independent 64-element beams in either TX or RX modes. PAAM-level measurement results over the air without calibration show +/− 50° beam scanning with >10dB silde-lobe rejection

This article discusses the benefits and challenges associated with the design of multi-function scalable phased arrays at millimeter wave frequencies. First, applications for phased arrays with tens to hundreds of elements are discussed. Existing solutions for scaling silicon-based phased arrays from microwave to terahertz frequencies are reviewed. The challenges and tradeoffs associated with multiple integration options for W-band phased arrays are analyzed, with special consideration given to packaging and antenna performance. Finally, a solution based on SiGe ICs and organic packages for a 64-element dual-polarized 94 GHz phased array is described, along with associated measurement results.

An organic-based multi-layered phased-array antenna package for a 28GHz 5G radio access applications is hereby introduced. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct antenna probing measurements of the package show over 3GHz bandwidth and 3dBi gain at 28GHz. A phased array transceiver module has been developed with the package and four SiGe BiCMOS ICs are attached using flip-chip assembly. Module-level measurements in TX mode show 54dBm EIRP and near-ideal 35dB gain increase for 64-element power combining. 64-element radiation pattern measurements are reported with a steering range of > ±40 degrees without tapering in off-boresight direction.

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves

To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

This paper explores the electrical performance of a recessed probe launch (RPL) technique for measurement of embedded (internal) printed circuit board (PCB) structures such as striplines and vias (plated through holes). The RPL uses high-frequency microprobes in combination with a milling technique that removes upper board layers and exposes internal probing points. A two-tier calibration technique is applied for the extraction of the S-parameters of the RPLs with the help of thru-reflect-line calibration standards designed on PCB. Full-wave models are used to corroborate and validate the obtained S-parameters. Good model-to-hardware correlation is obtained up to 40 GHz. Furthermore, the launch performance with respect to microprobe positioning and variations of the cavity size is investigated using the full-wave models. These simulations suggest techniques for launch optimization and probe modifications that improve the launch measurement bandwidth.

This paper presents issues and practical solutions for SIW designs with very thin substrate with high profile metal roughness at mmWave frequencies.

This paper studies the accuracy of the physics-based via model, specifically when applied to dense via arrays. The physics-based model uses Green's functions for cylindrical waves in radial waveguides to model the via return current paths and the coupling between vias. The effects of approximations made in this model are studied with regard to four types of modes based on an eigenmode expansion for the radial waveguide. It is found that for the mode conversion in the vicinity of the via, an accurate consideration of nonpropagating modes becomes critical with an increasing cavity height. For the interaction between vias in dense arrays, anisotropic modes have an impact for small pitches, whereas the coupling by nonpropagating modes is small for practical printed circuit board dimensions. For a data rate of 20 Gb/s, conclusions with regard to the applicability of the physics-based via model to a multilayer structure are drawn. For 80-mil pitch, a good agreement to full-wave results can be observed. Measurements have been carried out to validate this finding. For 40-mil pitch, the accuracy of the physics-based via model is not sufficient for data rates of 20 Gb/s or higher.

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.

A comprehensive overview is given of the strengths, limitations, and applicability of the short-pulse propagation technique (SPP). SPP is shown to be able to extract the broadband characteristics of a wide range of interconnect technologies found in digital computer applications and generate causal predictive models. Examples are given of such applications from on-chip wiring, ceramic and organic chip carrier, cards, boards, to cables, and structures with large inhomogeneities, such as found in differential and microstrip cases, irregularities (such as introduced by roughening of metallization), and various operating conditions, such as variable temperature and humidity. The use of SPP as a virtual test bench is explained and showcased through the analysis of the impact of manufacturing tolerances and via stub length on the electrical characteristics. The diverse versatility of the SPP method is discussed through many examples on practical interconnect structures with special emphasis on printed circuit board wiring.

Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.

This paper reports major improvements to a 3-D full wave solver for a microstrip line and through-hole via in layered media. The interior layer problem, consisting of vias between two reference planes, is solved using the Foldy-Lax multiple scattering equations. The exterior layer problem is solved using the method of moments (MoM) with the layered media Green's functions. The exterior layer and interior layer problems are combined to obtain the S-parameters of the trace and through-hole via. A fast approach for calculating the layered-medium Green's functions using the numerical modified steepest descent path method is utilized. The Green's functions require milliseconds to compute per point. Schemes for efficiently computing image contributions for the static portion of the mixed potential Green's function are also implemented to solve the neighboring or self-RWG (basis function) interaction in the MoM problem. To validate the accuracy of the solution, extensive comparison with Ansoft's HFSS versions 9 and 11 for different pad sizes and antipad sizes are presented. The CPU per frequency is also tabulated to demonstrate the speed of the approach in this paper.

This paper presents a low-cost antenna-in-package (AiP) design that supports broadside and end-fire direction radiation suitable for future 60 GHz portable applications. The package is based on multilayer organic technology, so it can be fabricated by PCB manufacturers.

This paper describes the demonstration of a millimeter-wave package for a fully-integrated switched-beam 60-GHz CMOS transceiver IC. The package supports differential transmit and single-ended receive paths in both broadside and end-fire directions with four integrated antennas. The multi-antenna configuration provides flexible link coverage with a small form factor suitable for portable communication devices. The 11mm × 11mm × 0.5mm package has 38 BGA pins and is built with low-cost printed circuit board technology using 4 metal layers and organic dielectric materials. Full-wave electromagnetic simulations were performed to verify antenna performance in the context of a full-package environment, including power/ground planes and signal wiring of the package and of the second-level PCB. System-level characterization results with a fully assembled transceiver module are presented, including measured antenna radiation patterns.

This article presents a full-wave electromagnetic approach for analyzing the electrical performance of massively coupled through silicon vias (TSV). The TSVs are modeled with SiO2 insulation coating and are placed in the sandwiched SiO2-Si-SiO2 substrate. The planar guided wave is analyzed to determine the fundamental mode and high order modes in stratified media. Cylindrical wave expansions and Foldy-Lax equations for multiple scattering techniques are adapted to the TSV problems. The effect of SiO2 coating around the via is modeled by the general expression of T-matrix coefficients. Both dispersive silicon loss and copper loss are included in this approach. Numerical simulation of a 4-by-4 TSV array is demonstrated to show the signal performance and crosstalk. It shows that the coupling issues among the TSVs will become significant beyond 15 GHz. The results are in excellent agreement with general purpose field solver. V C 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1204-1206, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/ mop.26021

This paper reports on modeling of simultaneous switching noise (SSN) in 3D TSV-based system with multiple IC chips stacked and connected through TSVs. TSVs and other components are modeled using full-wave electromagnetic tools to extract equivalent circuit models. Power distribution network (PDN) combining on-chip and off-chip components are simulated with SPICE. The voltage noise generated by switching current is analyzed to exanimate the impact of TSV geometric parameters such as TSV dimensions, pitch, and number. The current noise in TSV is also extracted for the potential impact on signal integrity. The impacts of TSV geometric parameters on the PDN noise are limited impacts at frequencies below 1 GHz. However, the frequencies of inter-chip resonances are sensitive to TSV geometric parameters. These resonant frequencies are often in the range of 1 GHz - 10 GHz, which may coincide with the clock frequency and induce significant noises.

This paper reports on modeling of simultaneous switching noise (SSN) in power distribution network (PDN) for 3D systems, where multiple IC chips are stacked and connected by through-silicon vias (TSVs). The noises generated by current switching during the transition from idle state to active state are analyzed with both on-chip and off-chip PDNs. SSN is decomposed into different frequency components and their characteristics are discussed. The switching noises in active and silent chips are extracted to evaluate the noise interference in a 3D chip stack. Decoupling capacitors and stagger intervals are used to suppress the noise. Modeling the PDN to minimize the switching noise effects based on our hybrid approach is demonstrated to be effective to analyze the 3D PDN and understand the design tradeoffs in 3D architectures.

Substrate noise coupling in 3-D CMOS SOI technology is characterized using hardware measurement. Couplings between device contacts and through-silicon vias (TSVs) are measured in frequency domain. Time domain simulations based on the measured S-parameters are performed to assess the impact of TSV-induced noise coupling on active circuit performance. Equivalent circuits are constructed with good model-to-hardware correlation. The characterization results demonstrate a dominant noise-coupling path through N+ epi layer in the SOI substrate. The data also successfully validates our proposed noise mitigation technique of using CMOS process compatible buried interface contacts, e.g., achieving over 20-dB reduction for TSV-induced substrate noise coupling at 1 GHz.

Common mode noise associated to the differential signal propagation represents a major concern for crosstalk and EMI issues. The common mode filter based on electromagnetic band-gap (EBG) structures have been shown to be cost effective and easy to design, since they are made using the standard PCB technology. The coupling between the differential interconnect and the EBG cavity converts the energy associated to the common mode into the cavity resonant mode, thus reducing the common mode noise reaching the receiver. A simple design procedure is reviewed in this paper for a quick design, and it is applied to a 8 GHz filter. The filter is then manufactured on a 6 layer PCB and its performances are investigated through measurements both in frequency and time domain. The filter topology as well as the design procedure are validated through model-to-hardware correlation..

This paper presents a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band. 32 receive elements and 16 transmit elements with dual outputs are integrated to support 16 dual polarized antennas in a package. The IC further includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level. The fully-integrated transceiver is fabricated in the IBM SiGe BiCMOS 0.13um process, occupies an area of 6.6×6.7mm2, and operates from 2.7V (analog/RF) and 1.5V (digital) supplies. Multiple operating modes are supported including the simultaneous reception of two polarizations with a 10GHz IF output, transmission in either polarization from an IF input, or single-polarization transmission/reception from/to I&Q base-band signals (2.5W RX, 2.9W TX). Measurement results show 8dB receiver NF and 2dBm transmitter output power per element at 94GHz in both polarizations.

This paper reports on modeling of the power delivery in TSV-based 3D systems, i.e., vertically integrated ICs with uniformly-distributed high-aspect-ratio through-silicon vias (TSVs). The voltage drop and di/dt noise are modeled to evaluate the impact of TSV density and TSV aspect ratio (AR). The frequency dependency of TSV parasitics is modeled with fullwave EM simulator, and the performance of the power delivery network (PDN) is analyzed in the frequency domain. PDNs with low-AR and high-AR TSVs are compared for trade-off analysis in terms of power delivery performance and TSV area occupation, which is critical for the design of TSV-based 3D power delivery.

This paper reports on power delivery modeling for 3D systems where through-silicon vias (TSVs) are not uniformly distributed, but are arranged at the peripheries of circuit blocks and die edges. The voltage drop (IR) and di/dt noise on the power delivery are modeled and compared with those given by uniformly distributed TSVs. The impact of TSV density and circuit block size, and their tradeoffs are evaluated.

This paper reports on the evaluation of high-speed signaling performance of multilevel metallic interconnects on glass substrates. The wafer fabrication, transfer process, and passive electrical characterization of interconnects are addressed. Measurement results demonstrate less than 5 dB/cm insertion loss below 20 GHz. Moreover, 2-level wiring on glass with inter-level vias is utilized to implement 3.6-mm long transmission lines that connect high-speed transceivers and optoelectronic devices in a VCSEL-based optoelectronic fiber link. The relative performances of diverse configurations with and without wiring on glass are compared. Error-free link operation at a bit-error-rate (BER) of 10-12 is demonstrated up to 30 Gb/s with ~3 dB sensitivity penalty for the link with glass carrier transmission lines.

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base highperformance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide layer, a highly doped N+ epi layer used for deep trench devices is taken into account in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low impedance ground return path can be readily created for effective substrate noise reduction in 3D IC design.

This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.

This paper presents the applications of a statistical and parametric link simulation environment (SPLSE) in modeling and characterizing server backplane channels. Model-to-hardware correlation is demonstrated for a 15-inch 3 Gb/s single-ended channel and an 18-inch 12 Gb/s differential channel, respectively. Hardware validated equalization schemes are further applied to demonstrate error free NRZ signaling at 25 Gb/s for the rehabilitated 18-inch differential channel with a lower-loss dielectric material.

It is important to understand how to deliver power into 3D heterogeneous systems, which require different power supplies for different components (e.g., digital, analog, mixed-signal, MEMS parts). This paper reports on a study for a simplified case, where the two power supplies with different voltage levels are uniformly distributed through a TSV-based 3D system. In addition to intrinsic voltage losses along the interconnections, we investigated for the first time the power noises due to electrical couplings between the multiple power supplies. We evaluated the through-silicon-via (TSV)-based 3D power delivery networks by combining the electromagnetic (EM) and SPICE simulations. With this hybrid approach, we first partitioned the 3D system into a number of elements, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit to characterize the 3D power distribution networks.

While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (V dd )variation over time for 3D systems in a manner of maximum accuracy and efficiency.

Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several advantages for power delivery, and this work investigates the impacts of decoupling capacitors on through-silicon-via (TSV)-based 3D power networks using a novel hybrid modeling approach, i.e., combining electromagnetic (EM) and SPICE simulations. We first partitioned a 3D system into a number of components, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit. Through comparing and analyzing the effectiveness of several decoupling strategies, design tradeoffs are made in selecting the proper values and placement of decoupling capacitors to ensure optimal power distribution solution in 3D architectures.

In the first article of this series, principles and methods of physics-based via modeling were discussed. It was shown how the electromagnetic behavior of vias can be captured by an equivalent circuit based modeling approach that describes all relevant full-wave effects. In this follow-up article, the authors present an approach to integrate striplines into the physics-based via model. The striplines can be located at any layer of the stackup and they may constitute both single and multiconductor transmission lines. The integration of striplines extends the via representation to a full, efficient interconnect model of, for instance, printed circuit board signal links. An intuitive integration approach at a circuit simulator level and application examples are discussed in this article as well.

For fast analyses of multilayer printed circuit boards and packages, the parallel-plate impedance (Z pp ) is often used in equivalent-circuit via models to describe the current return path for vias traversing a power/ground plane pair. Analytical algorithms for the Z pp calculation, such as the radial waveguide method, usually assumes solid planes and neglect the effect of multiple scattering among open via ports. However, this scattering can become significant when other vias lie in close proximity. Disregarding this fact can lead to potential passivity violations, especially for dense via arrays. We propose to use a new formulation for the Z pp calculation based on the contour integral method that takes the multiple scattering effect into account to resolve the passivity problem. A via array example is demonstrated and, in particular, the passivity issue is discussed.

Two differential stripline configurations with pitches of 8µm and 22µm are designed for ultra dense interconnect on silicon carrier. The transmission lines are implemented using four wiring levels to support chip-to-chip communication at 11.5Gb/s data rate over 2cm without equalization. Loss characteristics are extracted from test coupons with good model-to-hardware correlation. Impedance and temperature dependent loss performance are analyzed with simulation. Crosstalk performance between two pairs with and without ground shielding, as well as between two twisted pairs, are also evaluated with hardware measurement.

The effects of geometric asymmetry on the electrical performance of multi-channel differential signaling in printed circuit boards are investigated in this paper. The asymmetry, which is the origin of noise coupled through mode conversion, is difficult to control in real channel structures, where a large number of vias and traces are populated. Supported by an efficient parametric simulation tool, this paper presents the effects of the asymmetry on mode conversion and differential mode crosstalk in real multi-channel structures. This extensive parametric study was used to define design guidelines to suppress this noise coupling by adding ground vias in strategic locations.

In this paper the authors present a novel multiport probing fixture for high frequency measurements of dense via arrays. The probing fixture consists of a 36 mm by 36 mm multilayer printed circuit board plugged into an LGA socket clamped down to the device under test using custom hardware. The test signal is launched from top surface mounted coaxial connectors and fanned in with striplines to a 1 mm via pitch on the bottom side. Custom calibration substrates are used to deembed the probing fixture from measurements by applying multiport deembedding techniques. The effect of contact pressure on obtaining reproducible measurements is investigated.

In this paper the bandwidth limitations of two types of multiport probing fixtures for measurements of high density via array structures are investigated. Using a two-tier calibration technique and custom-made calibration substrates, error parameters for the probing fixtures were extracted and used to evaluate variability in measurements and substrate correction parameters. Results show adequate repeatability of the obtained error parameters up to 20 GHz. Digital links were measured utilizing these probing fixtures and results were compared to S-parameter measurements using RF microprobes. Good correlation up to 10 GHz – 15 GHz was established when compared to microprobe based measurements of link structures with stub access vias. For link structures with through access vias the adequate correlation bandwidth was founded to be 5 GHz – 10 GHz.

This paper reports on a number of extraction techniques to investigate the TSV parasitics in 3D integration/packaging, including 3D fullwave electromagnetic (EM) simulator, 3D quasi-static EM simulator, static SPICE simulator, and empirical calculations. All the TSV RLGC values extracted from the fullwave simulation are in good agreement among different approaches over the entire frequency range of interest. Empirical calculations indicate close results to fullwave extractions, while the quasi-static simulation underestimates TSV parasitics. A wideband SPICE model is generated from TSV EM solution with good agreement for both magnitudes and phases of return loss and insertion loss. Further sensitivity analysis results indicate the isolation layer thickness weighs most in the signal gain at 20 GHz. This work provides some insight to TSV electrical characteristics and helps TSV physical design to maximize the benefits of 3D systems.