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The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a “gearbox” LSI-which switches between 10×10Gb/s data signals on the physical-coding-sublayer side and 4×25Gb/s data signals on the physical-media-dependent side. A gearbox LSI based on 0.13 μm SiGe BiCMOS consumes 8W of power [2], which is about half of the total power consumption of the optics module. Aiming to reduce the power consumption, a 50Gb/s 2:5 DEMUX based on CMOS technology is developed [3]. In addition, since the architecture in reference [2] consists of two LSIs (MUX and DEMUX), loop-back operation, which is required in the IEEE standard, is impossible. In response to these circumstances, we have developed a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI — implemented in 65nm CMOS — decreases power dissipation by 75% compared to that of a conventional LSI.

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10-12 BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.

The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

A CDR circuit and a phase detector are the key building blocks of high-speed interconnect systems. Today, most CDR circuits use bang-bang phase detectors. These phse detectors have several advantages, including low power consumption, a simple circuit structure, and compatibility with digital circuits [1,2]. However, bang-bang phase detectors have the intrinsic drawback of large quantization noise. Therefore, the CDR loop bandwidth must be relatively low to mitigate the effect of the quantization noise by time averaging. In particular, digital CDRs operated in a Δ-modulation loop are susceptible to quantization noise. On the other hand, linear phase detectors (LPDs) do not exhibit quantization noise and therefore by using them one can potentially increase the CDR bandwidth to achieve improved jitter tolerance. However, conventional LPDs, such as the Hogge phase detector, which detect the phase difference as a pulse width, cannot be easily incorporated in a digital CDR [3]. In this paper, a 10Gb/s receiver is described that is equipped with a track-and-hold-type LPD as well as a charge-redistribution ΔΣ modulator for incorporation in a digital CDR. The 10Gb/s receiver exhibited low quantization errors and high loop bandwidth that are due to the use of a linear phase detector while it maintains the advantages of a digital CDR circuit, such as low power consumption, small area occupation, fast locking time, and a low-jitter recovered clock because an internal VCO is not needed. The tracking bandwidth of the CDR circuit is about 20MHz, and the power consumption of the receiver is 65mW

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).