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This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level.

This paper explores and discusses various design considerations for inverter-based systems. Different load sharing techniques are presented for the integration of renewable energy sources within islanded microgrids. In off-grid connection, renewable energy sources are often configured to share power based on their rated capacity. This paper explores both conventional and dynamic load sharing interaction between distributed generation units, both in an inductive (high voltage) and resistive (low voltage) networks. Load sharing based on the proper design of virtual impedance is also reviewed.

The compact model of an injection enhanced insulated gate bipolar transistors based on the exponential solution of the ambipolar diffusion equation is presented in this paper. To model plasma carrier distribution, an exponential shape function is used, and in steady-state forward bias operation, the plasma carrier concentration has a distribution of catenary form with just two exponential basis functions, while in transient operation, more complex profiles can be approximated using a number of exponential basis functions with a range of decay length parameters, shorter than the steady state ones. The device model developed has been implemented in Saber circuit simulator and successfully tested against complete set of high current, high voltage experimental results.

In this paper a novel photovoltaic (PV) emulating scheme for testing maximum power point tracking (MPPT) algorithms and PV inverters has been proposed. It is constructed by the parallel connection of conventional solar panels with a DC power supply operating in current source mode. The advantages of the proposed scheme are cost-effectiveness, relatively easy implementation and indoor testing of MPPT algorithms and power converters avoiding weather and time of day dependency on solar irradiation levels. Furthermore, the proposed PV emulator avoids the bandwidth problem associated with the dc converter based PV emulating systems. Detailed circuit connection, parameters, electrical characteristics and mathematical model of the PV emulator are presented and discussed. Proposed PV emulating system has been used to test a boost DC/DC converter controlled by Perturb & Observe (P&O) MPPT algorithm. Test results confirmed the effectiveness of the proposed PV emulation system and all achieved results correspond well to the original designed values.

The paper aims to review the research area of the IGBT compact modelling and to introduce different device models. The models are separated in two groups, one that solves ambipolar diffusion equation (ADE) and one that does not. Both types of compact models have been successfully used in the past for power electronic circuit design.

This paper explores the use of a dynamic virtual impedance approach to load sharing as an alternative to the more generic droop load sharing scheme for low-voltage islanded micro-grids. The approach is based on taking advantage of the power decoupling capability of the virtual impedance scheme to facilitate appropriate load sharing based on the available generation capacity of distributed generation (DG) units. The proposed scheme identifies the DC operating zone of the photovoltaic inverter-based unit as irradiance levels change and conditions the virtual impedance loop for an efficient load sharing based on available generation. This dynamic approach allows taking into account the rating, output impedance and voltage limits of each unit. The proposed scheme provides energy saving; since energy demand from a local auxiliary generator is reduced. Results from the proposed dynamic scheme were tested on a P-f/Q-V droop, in the presence of virtual impedance, and results were compared with the conventional-static virtual impedance loading method. The proposed method is validated using MATLAB/SIMULINK simulations.

The physics-based IGBT sub-circuit compact model which can successfully include the effects of the localized lifetime control (LLC) on device electrical performance has been described in this paper. The model of non-punch trough IGBTs with different locations of LLC region is developed and its accuracy is verified based on the agreement with the results of two-dimensional numerical simulations of LLC effects in IGBTs. The models have been implemented in SPICE for investigation of the total power losses in the single phase Pulse Width Modulated (PWM) inverters.

In this article, a high-speed electro-thermal (ET) modelling strategy to predict the junction temperature of insulated gate bipolar transistor (IGBT) devices of a three-phase inverter power module is presented. The temperature-dependent power loss characteristics of IGBT and diode devices are measured and stored in lookup tables, which replace the conventional complicated physics-based compact models. An inverter is modelled as a voltage controlled voltage source, which allows the inverter-based power train simulation to be carried out in the continuous time domain with a large simulation time-step (1 ms). Using the simulated sinusoidal voltage and current components of the inverter output, the given pulse width modulation mode, the conduction time (duty ratio) and the current of the devices are extracted. Based on the lookup tables, on-times and conduction currents of devices, the average power loss over each simulation time-step is calculated, which is then fed into the inverter thermal model to predict...

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-/spl mu/m CMOS technology.

A two-dimensional (2D) physical compact model for advanced power bipolar devices such as Injection Enhanced Gate Transistor (IEGT) or Trench IGBT is presented in this paper. In order to model the complex 2D nature of these devices, the ambipolar diffusion equation has been solved simultaneously for different boundary conditions associated with different areas of the device. The IEGT compact model has been incorporated into the SABER simulator and tested in standard double-pulse switching test circuit. The compact model has been established to model a 4500 V–1500 A flat pack TOSHIBA IEGT.

New compact models of the IGBTs (both non-punch through IGBT (NPTIGBT) and punch-through IGBT (PTIGBT)) are presented in this paper. The models are implemented in the SABER circuit simulator and used for a study of IGBT anode current and voltage characteristics during a device turn-off (clamped inductive load circuit with gate controlled turn-off), since these parts of the transient characteristics essentially predict the power dissipation ( V × I ) inside the device. It is shown that PTIGBTs are faster than NPTIGBTs, this becoming more apparent at higher clamp voltages.

Physically based compact device models of the MOSFET, as well as PiN diode and insulated gate bipolar transistor (IGBT) are presented in this paper. For the correct description of static and dynamic behaviour of power bipolar devices (IGBT and PiN diode) a 1D module for the drift zone (low doped n-base region) is presented that incorporates conductivity modulation and non-quasistatic charge storage effect. Finally, it is possible to transform, relatively easily, these electric models into the electrothermal models by adding an extra node (thermal node) to the electrical compact models. This thermal node will store information about junction temperature of the active device and it represents a connection between the device and rest of the circuit thermal network.

Mechanical stress related instabilities in silicon bulk material under integrated circuit (IC) metallization are investigated. The test structures based on Wheatstone bridge configuration in which two out of four resistors were covered by wide aluminium stripes were fabricated especially for this purpose. Calculations based on the piezoresistance effect were utilized to estimate the mechanical stress in the silicon substrate. Also, finite element modeling (FEM) of the fabricated test structures has been performed. Both results, experimental and numerical, show that metallization involves an additional stress term. In the silicon buffer, The piezoresistance can influence the matching characteristics of ICs and also produce a time-drift of IC performance due to the time-drift of mechanical stress. Resistance mismatching of more than 1000 ppm was measured when the resistors were covered by aluminum. A covered resistance drift of 245 ppm due to aluminum plastic deformation was measured when heating tests mere applied. Finally, the simulation results for the prediction of the stress levels in silicon covered with metal lines of various widths are presented. For a 4 /spl mu/m-width aluminum line it was recognized a safe distance of 10 /spl mu/m.

A novel method for extraction of model parameters based on neural networks is presented and exemplified through its application to extraction of ON-state model parameters of power VDMOSFETs. The method can be widely and efficiently used for parameter extraction of ON-state and transient analytical models for a large class of microelectronic devices.

As penetration of distributed generation increases, the electrical distribution networks may encounter several challenges mainly related to voltage control. The situation may deteriorate in case of a weak grid connected to an intermittent source such as photovoltaic (PV) generation. Fast varying solar irradiance can cause unacceptable voltage variations that may not be easily compensated by slow-responding utility equipment. The PV inverter can be used to control the grid voltage by injecting/absorbing reactive power. A small-signal model is derived in order to study the stability of a PV inverter exchanging reactive power with the grid. This paper also proposes a method that utilizes the available capacity of the PV inverter to support the grid voltage without violating the rating of the inverter and the maximum voltage that the inverter's switching device can withstand. The method proposed in this paper is validated using PSCAD/EMTDC simulations.

A combination of two conventional junction isolation structures is used to produce a device, which significantly improves the blocking of minority carriers injected into the substrate of a power IC due to switching of an inductive load. Simulation results show that the connection scheme employed greatly enhances the efficiency of the structures. A substrate current reduction of up to four orders of magnitude compared to conventional junction isolation structures is achieved. The significance of doping profiles in the p-sinker region is evaluated.

A simple method for the extraction of power VDMOS transistor parameters, based on the combination of the drain current and transconductance transfer characteristics in both linear and saturation regions, is presented. Reliable values of five parameters necessary for the complete description of the output I-V characteristics are obtained.

Almost all of the Maximum Power Point Tracking (MPPT) methods for photovoltaic (PV) systems are based on searching algorithms. Searching algorithms require relatively complex control schemes and reduce the speed and accuracy of the MPPT method. This paper proposes a novel MPPT method which aims to circumvent traditional searching algorithms thus increasing the speed and accuracy of the response to varying irradiation levels. The method will be validated through MATLAB-SIMULINK simulations. (5 pages)

A case study regarding development of a 100V Power IC technology is presented in this paper. A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon. Different electrical isolation schemes have also been investigated.

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.

An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit.

A load current observer based feedforward control scheme for three-phase voltage source pulse width modulation (PWM) active rectifiers is presented. The observer is designed to identify the load current disturbance, which is then forwarded to an inner current controller. Details of the design of the inner current controller and outer dc voltage regulator are also presented. To cope with the delay time of the digital control loop, Smith-predictor is employed in the current control loop to stop overshoots and oscillations during transient current regulation. Simulation model has been set up using commercially available VisSim software and then implemented in a digitally controlled prototype of a three-phase PWM active rectifier. The simulation and experimental results show that without using an actual load current sensor, the proposed observer based feedforward control scheme provides almost the same performance as the traditional feedforward control based on actual load current measurement.

A novel method of obtaining sensorless speed information of induction motors, derived from current space vector amplitude fluctuation (SVAF), is presented in this paper. The space vector amplitude fluctuation associated with the eccentricity harmonics is first demodulated using Park transformation in space vector plane. Short Time Fourier Transformation (STFT) is then carried out to estimate the speed of an induction machine running under transient conditions phase such as motor starting. The method has been tested and verified on an ABB 2-pole induction machine in laboratory; excellent agreement has been achieved between the estimated speed using the proposed scheme and the measured speed using an actual speed sensor. The advantage of the proposed method is that it is more effective to estimate the motor speed running with high acceleration rate during motor starting.

In this paper, we present investigations performed on 4H-SiC surfaces annealed at high temperature in the presence of a protective carbon cap and compare these to samples fabricated by the same process, but without a protective layer. The high temperature treatment resulted in sample surfaces with various roughnesses. The annealed samples have been oxidised to fabricate MOS structures in order to investigate the effect of annealing on the physical properties SiO2/SiC interfaces. Structures have been characterized using C-V measurements. Results suggest that treatments to reduce surface roughness caused by annealing, prior to any oxidation, are effective in reducing the density of interface traps. The density of SiO2/SiC interface traps for samples treated prior to oxidation is lower than interface trap densities for annealed samples with no preoxidation roughness reduction treatment.

A compact thermal model of a three-phase IGBT inverter power module utilised in most of variable speed drivers has been described in this paper. The compact thermal model equals to an electrical RC network model is assembled from thermal resistances and thermal capacitances so that it can be easily implemented in a circuit simulator. Transient thermal 3D finite element (FE) model of the IGBT module has been carried out using commercially available FLOTHERM software; the 3D simulation results are then utilised to extract the compact thermal network parameters of the IGBT power modular. Good agreement has been achieved between simulation and experimental measurement.

A study of the latch-up robustness for a new power IC technology involving Si substrate/wafer modifications is presented in this paper. The results shown confirm that for dual-well CMOS technologies, changes in the substrate/epitaxial layer structure are a satisfactory way of improving power IC process capabilities without compromising the CMOS performance. Both simulation and experimental results are presented.

The unified electro-thermal modelling of the IGBT and power PiN diode based on modified minority carrier drift- diffusion (DD) theory is described in this paper. PiN and IGBT models are embedded in PSPICE commercial simulation software and successfully tested against commercially available power devices.

A novel power PiN diode model is derived based on the generalised all-injection level minority carrier drift–diffusion theory. An equivalent lossy transmission lines describing the carriers transport trough arbitrarily doped emitter and base quasi-neutral regions are defined. The extended electro-thermal diode model including temperature dependences of carrier transport parameters is also described and implemented in circuit simulator PSPICE. By tuning a small set of model parameters, an excellent agreement of modelling results with numerical simulations of realistic power PiN diode is obtained for different switching conditions and temperatures.

An original work in developing technology that allows the integration of multiple vertical power devices within Power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability.

Fast power devices thermal simulation method based on averaging power losses over each cycle of PWM switching frequency is presented in this paper. For implementing a long real time dynamic thermal simulation of power devices, device power losses during transient process and static characteristics are defined as a function of device conduction current and junction temperature, and are represented by a lookup table. By carrying out the circuit electrical simulation, the device conduction current can be obtained. By combining the device conduction currents, global device temperature (GDT) and the data from the lookup table, the average power loss over each cycle of PWM switching frequency is then calculated for carrying out the thermal simulation. With the proposed method, a relative large simulation time step can be employed and simulation speed can be increased dramatically. The method is suitable for a long real time thermal simulation for complex power electronics systems.

In this paper, a comparison of gold, nickel and aluminium Schottky diodes fabricated on high-quality, single-crystal CVD diamond is presented. Different metals, such as gold, nickel and aluminium, have been deposited on the oxidised surface of an intrinsic diamond layer to serve as Schottky contacts, in order to investigate the physical properties of the different metal-semiconductor interfaces. A Cr-layer, followed by a subsequent Au deposition was used to form the ohmic back contact for the Au-Schottky diodes, whereas a Cr-layer followed by a Ni deposition formed the ohmic contact for the Ni and Al-Schottky contacts. Contacts have been characterized using I-V measurements. The gold Schottky contacts exhibited reverse leakage currents as low as 0.01 muA at a reverse voltage of -600V, rising to 10 -A at 1kV (without any periphery protection). Nickel and aluminium contacts exhibited lower reverse leakage currents and higher average breakdown voltages, whilst giving poorer forward conduction

Fast power devices thermal simulation method based on averaging power losses over each cycle of PWM switching frequency is presented in this paper. For implementing a long real time dynamic thermal simulation of power devices, device power losses during transient process and static characteristics are defined as a function of device conduction current and junction temperature, and are represented by a lookup table. By carrying out the circuit electrical simulation, the device conduction current can be obtained. By combining the device conduction currents, global device temperature (GDT) and the data from the lookup table, the average power loss over each cycle of PWM switching frequency is then calculated for carrying out the thermal simulation. With the proposed method, a relative large simulation time step can be employed and simulation speed can be increased dramatically. The method is suitable for a long real time thermal simulation for complex power electronics systems

An alternative CMOS manufacturing process architecture for implementing power integrated circuits that may be used for applications requiring a bridge topology is presented. A RESURF N-LDMOS high-side compatible power transistor was designed onto the new process using TSuprem4 and Medici TCAD software. Masks were designed using Cadence Virtuoso and the new structure was manufactured at X-Fab UK Ltd. The physical results show good transistor characteristics compatible for high-side applications. The Specific RDSon for the new device is 260mOmegamm2 and breakdown voltage for both high-side and low-side operation exceeds 100V

An advanced physics-based equivalent-circuit model of IGBT has been described featuring a high accuracy in predicting device electrical performance in real circuit applications. A SPICE Level 3 model is employed for simulation of the equivalent DMOSFET, while the voltage dependant drain- to-gate overlapping capacitance and drain ohmic resistance elements are modelled separately. The one-dimensional physics- based model of the low-gain BJT device is developed using the equivalent non-linear lossy transmission line sub-circuit. IGBT model is implemented in PSPICE circuit simulator and high accuracy of the model is demonstrated by comparing the simulation results with the electrical measurements of several test power circuits.

The paper discusses the impact of active junction isolation (AJI) structures on the switching speed of power MOSFETs embedded in a power integrated circuit. These structures are charge activated and so it is crucial to allow sufficient time for them to charge and discharge in order for them to become effective. A switching period longer than these relaxation times has the potential to result in severe on-chip charge build-up. The effect of grounding on the AJI performance has been investigated, since the effectivness of the active junction isolation techniques relies on changing locally the potential of the floating substrate in proximity of the carrier injection point.

A fast power losses calculation method for long real time thermal simulation of IGBT module for a three-phase inverter system is presented in this paper. The speed-up is obtained by simplifying the representation of the three-phase inverter at the system modelling stage. This allows the inverter system to be simulated predicting the effective voltages and currents whilst using large time-step. An average power losses is calculated during each clock period, using a pre-defined look-up table, which stores the switching and on-state losses generated by either direct measurement or automatically based upon compact models for the semiconductor devices. This simulation methodology brings together accurate models of the electrical systems performance, state of the art-device compact models and a realistic simulation of the thermal performance in a usable period of CPU time and is suitable for a long real time thermal simulation of inverter power devices with arbitrary load. Thermal simulation results show that with the same IGBT characteristics applied, the proposed model can give the almost same thermal performance compared to the full physically based device modelling approach. Copyright © 2006 John Wiley & Sons, Ltd.

This paper investigates the performance of single and multiple junction isolation structures for smart power IC’s with regards to transient carrier injection. Both, single and multiple isolation structures are produced using a standard CMOS process all using the same surface area. The devices are based on different active junction isolation principles and it is shown that combinations of these devices can significantly improve the blocking characteristics of the isolation without an increase in surface area. It is shown that the transient current rejection of the devices is markedly different from their dc blocking characteristics. Considerations for the design of efficient isolation structures are discussed.

A 0.6 /spl mu/m CMOS process was adapted to incorporate LDMOS transistors for Power Integrated Circuit Applications. The design was realised by adding only three additional ion implants process steps and one extra masking process step providing a cost effective approach. The design was optimised prior to manufacture by the Avanti TCAD simulation tool. Physical results show good agreement with the simulated device and display 2-D RESURF action.

An electro-thermal (ET) strategy used for ET circuit simulations is described in this paper. An original program for a MATLAB environment based on a deconvolution method is written and used for a determination of the RC dynamic thermal network parameters. An excellent agreement is obtained between experimental thermal transient response function of the device for a step function excitation and simulated one obtained using corresponding RC thermal network.

New dynamic electro-thermal models of the power MOSFET, and power bipolar devices (PiN diode and IGBT) are presented in this paper. Firstly, electric device models were made, and then they were transformed into the electro-thermal models by adding a thermal node. This thermal node stores information about junction temperature and represents a connection between the device and rest of the circuit thermal network. All models have been found to be efficient and robust in all cases examined.

A new physically-based compact device model of the PiN diode is presented. A one-dimensional model for the drift zone (low doped n-base region) is presented which accurately describes conductivity modulation and non-quasistatic charge storage effects within the structure. To validate the power diode compact model, simulation results are compared with those from a detailed drift-diffusion finite-element model, as well as with experimental results (for two different devices), showing an excellent agreement in all cases. The model is found to be efficient and robust in all cases examined.

Temperature and temperature variation cycles of insulated gate bipolar transistors (IGBTs) are important variables for reliability assessment of inverter power module (IPM) applied in hybrid vehicles. Conventional electro-thermal (ET) simulation based on physics device model has been considered as an accurate method, but it is difficult to conduct a long real-time (over 10 min) thermal simulation as required in hybrid vehicles. In this study, a fast ET simulation model for long real-time thermal simulation of three-phase IGBT IPMs is presented in which the consideration of inverter/motor power train modelling, determination of simulation time step, calculation of temperature-dependent power losses as well as thermal network are discussed in detail. The advantage of the proposed simulation model is the IGBT temperature and variation cycle with power cycles of vehicles can be simulated at a fast speed without significant loss of accuracy. Device temperature over 10 min of real-time operation for a three-phase IGBT IPM has been simulated and validated by an experimental test.

Practical results are used to parameterise a physically based, compact IGBT model for three generations of IGBT (PT, NPT and IGBT3), at temperatures extending down to 50 K. Full details are presented of the model parameter variations with temperature over the range 50-300 K. The models are then used to examine the performance of a sinusoidal pulse-width-modulated inverter leg at cryogenic temperatures.

This paper describes recent experimental work carried on the optimisation of junction isolation structures for use in Power Integrated Circuits. Isolation is required to collect minority carriers injected into the substrate before the can reach the low voltage control circuitry. The most effect form of isolation found in this paper combines A number of techniques (SJI & MAAP) to reduce the injected current by3 orders of magnitude compared with the standard junction isolation techniques.