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Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross-section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross-section curves without any beam results. Moreover, the current method of analyzing cross-section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supply-voltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this paper proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes.

Redundant pairs of SOI transistors have been utilized as a Radiation Hardening-By-Design technique. Their applicability was subsequently extended for analog circuits, such as current mirror circuits, and successfully demonstrated with a phase-locked loop circuit.

The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region in the SET current waveform generated in a struck transistor.

We describe proton induced bulk damage observed in 90 nm process SDRAM. The degradation of the data retention ability was evaluated. The effect due to the difference of process technology and memory cell structure was discussed. The result indicates that the value of the capacitance of the storage capacitor and the volume of the depletion region are key parameters concerning the failures caused by bulk damage.

We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 /spl mu/m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm/sup 2/).

We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.

A new failure mode that is attributable to the bulk damage caused by single protons has been reported in 256-Mbit SDRAMs. The refresh rate required to retain memorized data was measured as a typical parameter to detect the effect. We performed the proton irradiation test and discussed results regarding the influence of this failure.

New types of multiple-bit upset (MBU) modes have been identified in high density DRAMs (16 Mbit and 64 Mbit). The identification of the mechanisms responsible for the new modes is based on detailed physical bit-map analysis.

This paper describes the Single Event Effect test result on the Radiation Hardness-By-Design SRAM for 0.15µm Fully Depleted CMOS/SOI-ASIC fabricated by a commercial foundry. Sufficient immunity was demonstrated for the SEU/SET required for space applications.

In recent years, due to the demand for increased integration and device scaling, integrated circuits (ICs) have been designed with the design rule less than 100 nm. In these ICs, single-event upsets (SEUs) and single-event transients (SETs) are serious problems because their supply voltage and the threshold voltage of the transistors are decreased. A DICE memory cell is said to have excellent tolerance against SEUs. A DICE-based flip-flop with a SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated. Its improved performance was demonstrated through radiation testing and discussion was made in comparison with a TMR. SEU sensitivity for the angled irradiation was measured and discussed in this study. The test of edge-on irradiation was performed for the first time. The importance of the angled irradiation for the memory cells that have redundant memory nodes was demonstrated.

This paper describes Total Ionizing Dose and Single Event Effects test results of a Radiation Hardness-By-Design Library for 0.15μm Fully Depleted CMOS/SOI-ASIC at a commercial foundry. Reasonable data was obtained to improve the library.