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In this paper, level Shifter circuit is analyzed which is efficient for converting low-voltage digital input signal into high-voltage digital output signal. The circuit has a diagnostic current generation device by using a logic error correction circuit that work by identifying the input and output logic level .When input signal changes, circuit produce low power operation only because it can dissipate power at the operating current. For the comparative analysis of this error correction Level Shifter different methodologies are used which named as biasing for the level Shifter. Result shows that the circuit converts a 0.4-V input signal to 3-V output signal. Simulation results are carried out by using 0.35μm CMOS technology. Power dissipation is 34nW for a 0.4V at 10 kHz input pulse. General Terms Low power design, leakage power, power dissipation, delay.

The ability of an item to perform a required function under stated conditions for a specified period of time. The main objective of this work is to analyze and estimate the reliability of a transmission line and thirteen stage ring oscillator as interconnects using GPDK 45 nm CMOS technology. As we know that reliability basically depends on HCI NBTI, PBTI and TDDB. Basically in this paper for the performance analysis we have analyzed the results in terms of transient response, delivered power by every component and noise analysis on different incident of time. In this work the reliability factors are done by comparing power, delay and output voltage after a specific amount of time.

A capacitor-less low drop-out (LDO) regulator for SoC applications with buffer based compensation technique is proposed in this paper. The 1.6 V LDO with a power supply of 1.8 V is implemented in GPDK 0.18 μm CMOS technology and it achieves a PSRR of 70 dB up to 1 kHz for load currents up to 10 mA. It makes use of PMOS folded cascode error amplifier to lower the flicker noise. Simulation results verify that the proposed LDO is stable for a capacitive load from 0 to 30 pF and with a load capability of 10 mA and has a drop-out voltage of 200 mV. The layout of the design shows that the area acquired on the chip is approximately equal to 0.79 mm2.

Performance and reliability analysis tests the VLSI circuits over a prolonged period of time at different conditions. Therefore, performance and reliability of an inverter circuit and two CMOS gate interconnect circuit, a combination of two inverters connected with an RC model as an interconnect structure has been analyzed. Reliability in VLSI circuits depends on hot carrier injection, negative biasing temperature instability, positive biasing temperature instability and time-dependent gate oxide breakdown. Reliability is analyzed by comparing power, delay and output voltage. The complete analysis is done using 45nm gpdk (generic process design kit) in Cadence Virtuoso.