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Closed-loop brain-implantable neuromodulation devices are a new treatment option for patients with refractory epilepsy. Seizure detection algorithms implemented on such devices are subject to strict power and area constraints. Deep learning methods, though very powerful, tend to have high computational complexity and thus are typically impractical for resource-constrained neuromodulation devices. In this paper, we propose a compact and hardware-efficient one-dimensional convolutional neural network (1D CNN) structure for patient-specific early seizure detection. Feature extraction techniques and a novel initialization method based on the forward-chaining training and testing scheme are used to improve model performance. Our compact model achieves similar accuracy to that of support vector machines, the state-of-the-art method for seizure detection, while consuming over 20x less power.

First, existing commercially available open-loop and closed-loop implantable neurostimulators are reviewed and compared in terms of their targeted application, physical size, system-level features, and performance as a medical device. Next, signal processing algorithms as the primary strength point of the closed-loop neurostimulators are reviewed, and various design and implementation requirements and trade-offs are discussed in details along with quantitative examples. The review results in a set of guidelines for algorithm selection and evaluation. Second, the implementation of an inductively-powered seizure-predicting microsystem for monitoring and treatment of intractable epilepsy is presented. The miniaturized system is comprised of two miniboards and a power receiver coil. The first board hosts a 24-channel neurostimulator system on chip fabricated in a [Formula: see text] CMOS technology and performs neural recording, on-chip digital signal processing, and electrical stimulation. The second board communicates recorded brain signals as well as signal processing results wirelessly. The multilayer flexible coil receives inductively-transmitted power. The system is sized at 2 × 2 × 0.7 [Formula: see text] and weighs 6 g. The approach is validated in the control of chronic seizures in vivo in freely moving rats.

First, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low-latency automatic sleep stage classification in rodents is presented. The classification algorithm uses one EMG (electromyogram) and two EEG (electroencephalogram) signals as inputs in order to detect REM (rapid eye movement) sleep, and is optimized for low complexity and low power consumption. It is implemented in an on-board low-power FPGA connected to a multi-channel neural recording IC, to achieve low-latency (order of 1 ms or less) classification. Off-line experimental results using pre-recorded signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.86%, respectively, with the maximum latency of 39 [Formula: see text]. The device is designed to be used in a non-disruptive closed-loop REM sleep suppression microsystem, for future studies of the effects of REM sleep deprivation on memory consolidation.

We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 [Formula: see text] CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 [Formula: see text] effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV rms over the bandwidth of 1 Hz to 1 kHz. The 8.7 [Formula: see text] chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

We assess and compare the effects of both closed-loop and open-loop neurostimulation of the rat hippocampus by means of a custom low-power programmable therapeutic neurostimulation device on the suppression of spontaneous seizures in a rodent model of epilepsy. Chronic seizures were induced by intraperitoneal kainic acid injection. Two bipolar electrodes were implanted into the CA1 regions of both hippocampi. The electrodes were connected to the custom-built programmable therapeutic neurostimulation device that can trigger an electrical stimulation either in a periodic manner or upon detection of the intracerebral electroencephalographic (icEEE) seizure onset. This device includes a microchip consisting of a 256-channel icEEG recording system and a 64-channel stimulator, and a programmable seizure detector implemented in a field-programmable gate array (FPGA). The neurostimulator was used to evaluate seizure suppression efficacy in ten epileptic rats for a total of 240 subject-days (5760 subject-hours). For this purpose, all rats were randomly divided into two groups: the no-stimulation group and the stimulation group. The no-stimulation group did not receive stimulation. The stimulation group received, first, closed-loop stimulation and, next, open-loop stimulation. The no-stimulation and stimulation groups had a similar seizure frequency baseline, averaging five seizures per day. Closed-loop stimulation reduced seizure frequency by 90% and open-loop stimulation reduced seizure frequency by 17%, both in the stimulation group as compared to the no-stimulation group.

During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal–Oxide–Semiconductor (CMOS), in power and area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose a novel low-latency parallel Convolutional Neural Network (CNN) architecture that has between 2-2,800x fewer network parameters compared to State-Of-The-Art (SOTA) CNN architectures and achieves 5-fold cross validation accuracy of 99.84% for epileptic seizure detection, and 99.01% and 97.54% for epileptic seizure prediction, when evaluated using the University of Bonn Electroencephalogram (EEG), CHB-MIT and SWEC-ETHZ seizure datasets, respectively. We subsequently implement our network onto analog crossbar arrays comprising Resistive Random-Access Memory (RRAM) devices, and provide a comprehensive benchmark by simulating, laying out, and determining hardware requirements of the CNN component of our system. We parallelize the execution of convolution layer kernels on separate analog crossbars to enable 2 orders of magnitude reduction in latency compared to SOTA hybrid Memristive-CMOS Deep Learning (DL) accelerators. Furthermore, we investigate the effects of non-idealities on our system and investigate Quantization Aware Training (QAT) to mitigate the performance degradation due to low Analog-to-Digital Converter (ADC)/Digital-to-Analog Converter (DAC) resolution. Finally, we propose a stuck weight offsetting methodology to mitigate performance degradation due to stuck $R_{\text{ON}}/R_{\text{OFF}}$ memristor weights, recovering up to 32% accuracy, without requiring retraining. The CNN component of our platform is estimated to consume approximately 2.791 W of power while occupying an area of 31.255 mm2 in a 22 nm FDSOI CMOS process. [ABSTRACT FROM AUTHOR]

The advancement of implantable medical devices for the treatment of neurological disorders demands energy-efficient, low-latency processors for responsive, safe, and personalized neuromodulation. A 130-nm CMOS neural interface processor is presented to perform the brain-state classification and closed-loop control using programmable-waveform electrical stimulation. The architecture features an autoencoder neural network for both spatial filtering and dimensionality reduction. Dedicated feature extraction blocks are implemented for univariate (signal-band energy) and multivariate (phase locking value, and cross-frequency coupling) neural signal processing. The proceeding exponentially decaying memory support vector machine (EDM-SVM) accelerator employs these features for hardware-efficient brain-state classification with a high temporal resolution. An integrated digitally charge-balanced waveform generator enables flexibility in finding optimal neuromodulation paradigms for pathological symptom suppression. The system on chip (SoC) is validated using the EU human intracranial electroencephalography epilepsy data set, achieving a seizure sensitivity of 97.7% and a false detection rate of 0.185/h while consuming 169 $\mu \text{J}$ per classification. [ABSTRACT FROM AUTHOR]

Objective Sudden unexplained death in epilepsy is the leading cause of death in young adult epilepsy patients, typically occurring during the early postictal period, presumably resulting from brainstem and cardiorespiratory dysfunction. We hypothesized that ictal discharges in the brainstem disrupt the cardiorespiratory network, causing mortality. To study this hypothesis, we chose an animal model comprising focal unilateral hippocampal injection of 4-aminopyridine (4- AP), which produced focal recurrent hippocampal seizures with secondary generalization in awake, behaving rats. Methods We studied ictal and interictal intracranial electrographic activity ( iEEG) in 23 rats implanted with a custom electrode array into the hippocampus, the contralateral cortex, and brainstem. The hippocampal electrodes contained a cannula to administer the potassium channel blocker and convulsant (4- AP). iEEG was recorded continuously before, during, and after seizures induced by 4- AP infusion into the hippocampus. Results The control group (n = 5) was monitored for 2-3 months, and the weekly baseline iEEG recordings showed long-term stability. The low-dose group (1 μL 4- AP, 40 m m, n = 5) exhibited local electrographic seizures without spread to the contralateral cerebral cortex or brainstem. The high-dose group (5 μL 4- AP, 40 m m, n = 3) had several hippocampal electrographic seizures, which spread contralaterally and triggered brainstem discharges within 40 min, and were associated with violent motor seizures followed by dyspnea and respiratory arrest, with cortical and hippocampal iEEG flattening. The group that received high-dose 4- AP without brainstem implantation (n = 5) had similar seizure-related respiratory difficulties. Finally, five rats that received high-dose 4- AP without EEG recording also developed violent motor seizures with postictal respiratory arrest. Following visualized respiratory arrest in groups III, IV, and V, manual respiratory resuscitation was successful in five of 13 animals. Significance These studies show that hippocampal seizure activity can spread or trigger brainstem epileptiform discharges that may cause mortality, possibly mediated by respiratory network dysfunction. [ABSTRACT FROM AUTHOR]

A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 \mum CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 \muW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data. [ABSTRACT FROM PUBLISHER]