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Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.
- Source :
- IEEE Transactions on Biomedical Circuits & Systems; Oct2011, Vol. 5 Issue 5, p430-438, 9p
- Publication Year :
- 2011
-
Abstract
- A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 \mum CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 \muW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 19324545
- Volume :
- 5
- Issue :
- 5
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Biomedical Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 66820097
- Full Text :
- https://doi.org/10.1109/TBCAS.2011.2170686