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Degradation of (Ba,Sr)TiO[sub 3] during a forming gas anneal was examined and the effect of a SiO[sub 2] capped (Ba,Sr)RuO[sub 3] electrode was studied. All the samples were prepared by a rf magnetron sputtering technique and the forming gas (10% H[sub 2]+90% N[sub 2]) anneal was carried out at 400 °C for 30 min. The (Ba,Sr)RuO[sub 3] film directly exposed to H[sub 2] ambient was damaged severely, which resulted in the reduction and phase separation into BaO and Ru. On the other hand, the SiO[sub 2] capped (Ba,Sr)RuO[sub 3] film was not damaged during H[sub 2] annealing. By adopting the SiO[sub 2] capped (Ba,Sr)RuO[sub 3] as an electrode of (Ba,Sr)TiO[sub 3], the degradation of (Ba,Sr)TiO[sub 3] could be inhibited. SiO[sub 2] capping also decreased the extent of the reduction of a Pt/(Ba,Sr)TiO[sub 3]/Pt structured capacitor, which is known to degrade dramatically. It is believed that the major cause of the tolerance to the forming gas anneal is the blocking capability of SiO[sub 2] against the diffusion of reaction products such as H[sub 2]O. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Perovskite type conducting materials (Ca, Sr)RuO[sub 3] and (Ba, Sr)RuO[sub 3] were prepared by rf magnetron sputtering as bottom electrodes for (Ba, Sr)TiO[sub 3] thin film capacitors. The crystallinity, interface property, and electrical properties of the (Ba, Sr)TiO[sub 3] capacitor applying the perovskite oxide electrodes were investigated. The interface between the dielectric and the electrode were analyzed by high-resolution electron microscopy and Auger electron spectroscopy. The interface had a marked effect on the electrical properties of the (Ba, Sr)TiO[sub 3] thin films. Dielectric constant for the (Ba, Sr)TiO[sub 3] had considerable dependence on the thickness of interfacial layer. The leakage current density of the capacitor was sensitive not only to the structural match but also to the chemical match between (Ba, Sr)TiO[sub 3] and the electrode. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

In this study, a 2 in. Ni field aided lateral crystallization (FALC) polySi thinfilm transistor (TFT) (120 x 240) array was fabricated at the maximum process temperature of 500°C using an optimized current density distribution design. We investigated the correlation between crystallization and transistor characteristics in terms of transistor position in the array. Because an identical current density in the channel region of each pixel transistor was favorable to achieve uniform crystallization, an optimal common electrode design was chosen via Mathcad simulation. After the crystallization process, it was confirmed that the crystallinity variation in the transistor channels agreed well with the predicted simulation results. Furthermore, the positional variation in important transistor parameters in the array showed a good match with that of crystallization. The mean threshold voltage was 5.9 V (ΔVth = ± 0.2 V) while the mean mobility was 92.5 cm2 V1 s1 with a variation of 9.8%. These values suggested that the uniform NiFALC polySi TET arrays fabricated by the optimal design of the electrode were applicable to the active matrix organic light emitting display backplane. [ABSTRACT FROM AUTHOR]

Abstract: Characteristics of tantalum silicon nitride (TaSiN) thin films have been investigated as an electrode material for Ge2Sb2Te5 chalcogenide phase change material. The films were deposited by co-sputtering system in which the ratio of tantalum nitride to silicon was controlled by the plasma power on each target. The TaSiN films showed tunable resistivity from 260 to 560 μΩ cm with increasing Si content. From the evaluation of PRAM cell structures consisting of the TaSiN and the Ge2Sb2Te5, we found that the SET voltages are nicely correlated with the resistivity of the TaSiN. Moreover, the sensing margin (resistance ratio: R SET/R RESET) turned out to be good for practical application. [Copyright &y& Elsevier]