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The electrical stability of molybdenum disulfide (MoS2) transistors is crucial for their use in various applications. However, it is tricky to evaluate the inherent stability of MoS2 transistors because it is highly dependent on environmental conditions during measurement such as humidity, light, and electrical factors. We studied the threshold voltage instability under negative bias stress at a variety of temperatures in a vacuum and in the dark to eliminate any environmental effects. In particular, the measurement of transfer curves under stress is minimized in order to study the inherent instability of MoS2 transistors, even though the measurement of transfer curves is normally indispensable to check for the evolution of electrical instability. MoS2 transistors have high average effective energy when compared to conventional amorphous Si and oxide semiconductor transistors, which allows for adequate operation at high temperatures. (© 2014 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The application of ion gels as gate dielectrics having an excellent mechanical flexibility and high capacitance to molybdenum disulfide (MoS2) devices has been extensively studied; however, some issues remain unaddressed with regard to device stability such as gate leakage current, hysteresis, and bias stress instability. This study suggests a fabrication process for the ionic gating of the MoS2 device to enhance the device stability by laminating the ion gel film onto the MoS2 transistor using a cut‐and‐stick method and adding a passivation layer to remove unintentional parasitic capacitances generated by the capacitive coupling effect. The ionic gating MoS2 transistor fabricated via this process operates at a low voltage (<1 V) and exhibits superior electrical characteristics such as low gate leakage currents (≈10−11 A), high on–off ratio (>106), and low hysteresis (<0.05 V). To further investigate the device stability, bias stress instability of the ionic gating MoS2 transistor is examined. The charge‐trapping mechanism is the main cause of threshold voltage shifts under gate bias stress. [ABSTRACT FROM AUTHOR]