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Half Bridge Modular Multilevel Converter (HB-MMC), a sub-module of modular multilevel converter (MMC), is widely accepted voltage source converter (VSC) topology for high voltage DC (HVDC) systems. HB-MMC has a disadvantage that it did not limit, clear DC fault current and protect IGBT converter from damage. For confining DC fault current, it is necessary to place fault current limiter (FCL) in series with HB-MMC. In this paper, Author presents two novel fault current limiter i.e. IGBT based fault current limiter (IGBT-FCL) and Parallel RL fault current limiter. IGBT based FCL consists of IGBTs and diode which are connected in parallel to each other. IGBT based FCL perform two functions i.e. it circumscribe large DC fault current and also clear DC fault current. The RL circuit has connected in series with HB-MMC. Due to no zero crossing point in DC systems, Hybrid DC circuit breaker (HDCCB) has been connected in series with Parallel RL and HB-MMC to clear the fault instantly. IGBT based FCL confine the fault current to 4 kA from 14 kA which is 72% reduction in fault current and clear fault current within 14 ms. The parallel RL circuit confines the fault current to 3.6 kA from 14 kA which shows 75% suppression of maximum DC fault current. With the help of HDCCB, the fault is cleared within 18 ms. The PSCAD/EMTDC has been used for designing of HB-MMC, IGBT-FCL, Parallel RL circuit and HDCCB.

This paper proposes direct microcontroller interface circuit on Arduino platform, which is realized using the inductive sensors. The circuit is composed of two external resistors and two reference inductors resulting in four RL circuits. The microcontroller independently excites the two RL circuit on the primary side in order to measure the discharging time of voltage across each inductor. The discharging time of voltage across the inductors on the secondary side is measured similarly which is excited due to mutual inductance from the primary side. The technique of time-to-digital conversion from the built-in timer of microcontroller enables estimation of inductance value, which is compared with the actual value for self-inductance and mutual inductance circuits. Error analysis on the discharge time measurement are performed viz, parasitic resistance, parasitic capacitance on input–output ports along with ringing effects and relative quantization error. The resistance and inductance estimation with regards to varying time period of oscillation of crystal is performed to analyze the effect of oscillation frequency on estimation. The parasitic resistance and quantization effects both contribute to the non-linearity errors (NLE) which is investigated further experimentally. The optimum value of the resistance was observed to be 120Ω and 60Ω for the primary and secondary side respectively. For primary side, the current and power consumption is 29 mA and 145 mW respectively, while for the secondary side, the current and power consumption is 27.5 mA and 137.5 mW respectively. The maximum NLE of −0.18 %FSS and −0.24 %FSS has been observed for an inductance range of 1 mH–10 mH along both primary and secondary sides respectively, whereas for an inductance range of 10 mH–100 mH, the NLE achieved was 0.29 %FSS and −0.34 %FSS for the primary and secondary sides respectively. The future scope of the linear position displacement of the inductive sensor concludes the paper. Keywords: Microcontroller, Arduino UNO, Mutual inductance sensor, RL circuit

High-speed circuit breakers (HSCB) used in DC circuits are one of the basic elements of overload, short-circuit and electric shock protection. Such breakers are used in transport (trams, trolleybuses, subways and railways) in electric power supply facilities and in vehicles. The performance and capability of limiting the current depend on the HSCB design and solutions applied in it. The circuit parameters, particularly its inductance also affect the performance. Additionally, each DC breaking in the RL circuit is accompanied by overvoltages whose level depends on the circuit parameters and breaker design. The paper discussed the process of direct current breaking by magnetic blowout high-speed circuit breakers and factors that affect the HSCB performance, i.e. opening time and arcing time. The influence of the circuit parameters and HSCB design on the value of arc voltage is outlined. The results of laboratory tests of 4 types of high-speed circuit breakers produced in Europe are presented. The test results were used to analyze the effect of current changes in the short circuit on the time of current breaking and the value of switching overvoltages – arc voltage. The results of simulation of the short-circuit breaking in the RL DC circuit made at the rate-of-rise of current in the circuit are presented. Based on the tests and simulations, the current breaking times, values of arc voltage generated in this process and arc energy that is acquired and dissipated by the arc chamber are determined. The objective of the tests and simulations was to answer the question whether it is possible to turn off direct current quickly without generating high arc voltage values – overvoltages in the circuit and how di/dt changes should be formed by a high-speed circuit breaker to achieve the shortest possible time with the lowest possible arc voltage and its lowest energy

Purpose This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology. Design/methodology/approach Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type metal–oxide–semiconductor transistor and the transistor operating in the saturation region through the connection of the novel circuit structure makes a further improvement on the performance of the whole circuit. Findings This design is base on the 0.18?m process of BCD, and the new bandgap reference circuit is verified. The results show that the circuit design not only is simple and novel but also can effectively improve the performance of the circuit. Bandgap voltage reference is an important module in integrated circuits and electronic systems. To improve the stability and performance of the whole circuit, simple structure of the bandgap reference voltage source is essential for a chip. Originality/value This paper adopts a new circuit structure, which directly connects the two base voltages of the transistors with the resistor. And the transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of LDO regulator circuit, at last to realize the temperature control.

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL circuits satisfying the 1.2-V supply voltage ( ${V}_{\mathsf {DD}}$ ) requirement of the 65-nm technology node. The fabrication process is identical to the conventional 65-nm CMOS baseline process, in which copper NEM memory switches are formed by a dual damascene process.

In this study, a three-level hybrid dc/dc converter by integrating the full-bridge circuit, resonant circuit and three-level flying capacitor circuit is presented to achieve the main advantages of low-voltage stress of power devices, low circulating loss, low-voltage ringing on the rectifier diodes and low-output filter inductor for medium-voltage dc-based systems. Two full-bridge circuits are connected in series to effectively reduce the voltage stress of switches. Half-bridge resonant circuit shared the lagging-leg switches of full-bridge circuit is used and operated at fixed switching frequency to extend the zero-voltage switching (ZVS) range from low load to full load. Thus, the drawback of narrow ZVS range in the conventional full-bridge converter is improved. A flying capacitor is adopted to automatically balance input split capacitor voltages in each switching cycle without any additional active components or complexity control scheme. The circulating loss in the full-bridge circuit is reduced to zero by parallel connection of outputs of full-bridge circuit and half-bridge resonant circuits. Finally, the theoretical analysis and performance of the proposed converter are verified by the experiments with a 1.92 kW prototype circuit.

This paper presents a high step-up converter, which utilizes a three-winding coupled inductor and a rectified voltage-doubler circuit to obtain high step-up gain for fuel cells. The proposed converter functions as an active-clamp circuit, which relieves large voltage spikes across the power switches. Thus, power switches with low-voltage-rated can be utilized to reduce conduction losses and circuit cost. Energy stored in leakage inductances of the coupled inductor is recycled to the output terminal, resulting in efficiency improvements. In addition, the coupled inductor in the presented converter can also have extra windings in order to achieve higher voltage gain. Finally, a prototype circuit with an input voltage of 60V and an output voltage of 380V is developed for a 1000W-rated fuel cell power-generation system to validate its performance, and experimental waveforms and measured efficiency under different input voltages and output power level are demonstrated. Copyright © 2016 John Wiley & Sons, Ltd.

This paper describes wideband three-way Wilkinson power dividers using LC-ladder circuits. The proposed dividers consist of multi-section LC-ladder circuits between input and output ports, and their output ports are connected each other through external circuits composed of series RL circuits. By connecting the appropriate external circuits in accordance with the number of LC-ladder circuits, the proposed dividers can be realized extremely wideband operation. In order to verify the design procedure, wideband three-way Wilkinson power dividers are simulated and fabricated at VHF-band. As results of simulation and experiment, we can obtain broadband characteristics with a relative bandwidth of over 60%, which are near agreement with the theoretical results.

The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-circuit making capacity of the circuit breaker is expressed in peak value and not in RMS value similar to breaking capacity. A series resistor or super-excitation is used to control the peak value of the short-circuit current in the equivalent test circuit. When using a series resistor, a higher rating of circuit breakers leads to a higher thermal capacity, thereby requiring additional space. Therefore, an effective, optimal design of the series resistor is essential. This paper proposes a method for reducing thermal capacity and selecting the optimal resistance to limit the making current by controlling the DC time constant of the test circuit.

This paper proposes an accurate tunable-gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor-charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by an 10-bit digital code. The 1/x circuit was fabricated using a 0.1 8μm CMOS process . Its core area is 0.011m m 2 (144μm×78μm) and it consumes 278μW at VDD=1.8V and fCLK=1MHz. Its error is within 1. 7% at VIN=0.05~1V.

This paper proposes a mathematical model for electrical discharge plasmas between moving electrodes under ac condition, which happens in ac switching apparatuses. The modeling work is started by converting the problem to a conventional RL network that treats the arcing phenomenon as a black box and proposing a transient differential equation to represent the breaking arc process. A resistance–time relation model developed from the classic Mayr model is then proposed. A conceptual unit-arc approach is used to deal with the issue of variable arc length as the contacts move. Experimental data from ac contactor tests are used to approximate the resistance–time function by a nonlinear curve fitting. The model is solved computationally and compared with the experimental data. It is that the model adequately describes the breaking arc phenomenon.

This paper presents a new numerical simulation method to calculate transient voltage profiles of lithium-ion secondary batteries. The method employs circuit analysis of an internal equivalent electric circuit composed of an electromotive force, an LR parallel circuit, and eight CR parallel circuits. To demonstrate the accuracy and versatility of this approach, the authors measured the transient voltage responses of three types of test batteries with different output power densities, and compared these experimental data with simulation results. Battery performance was tested using different charge/discharge current patterns and a range of values for state of charge (SOC) and operating temperature. The accuracy of the proposed simulation method was confirmed for all test cases using the three different batteries and charge/discharge current patterns, demonstrating that the method is versatile and applicable to various lithium-ion secondary batteries regardless of type. Since the employed internal equivalent electric circuit is composed of only DC voltage source and linear R , L and C elements, all of general purpose software for electric circuit simulations can easily deal with the circuit. This advantage and the obtained results indicate that the proposed simulation method is a useful technique and offers a powerful tool to develop sophisticated battery control systems for various applications.

Voltage Balance of the series-connected dc-link capacitors is the key problem of three-level diode-clamped converters. In this paper, an auxiliary voltage balance circuit (VBC) is presented to maintain the voltage balance of dc-link capacitors. The voltage balance circuit consists of a clamping capacitor and a current-limiting inductor. With the clamping capacitor, the voltage stresses of the auxiliary circuit devices are restricted to one half of the bus voltage, and the current ripple of the inductor is also effectively suppressed. The operating principles of the auxiliary circuit are studied, and a time-domain model is derived. Accordingly, a control algorithm of the auxiliary circuit is proposed based on finite-control-set model predictive control. Simulation results validate the effectiveness of the auxiliary voltage balance circuit. The auxiliary circuit is applicable for three-level DCI-based energy conversion systems, static reactive power compensations and medium-voltage highpower motor drives.

For the study of switching transients in Extra High Voltage (EHV) networks it is common practice to model a relatively small part of the EHV network. The downstream network is either disregarded or modeled as a parallel RC or RL circuit, based on the powerflow, directly at the secondary side of the transmission transformer. In this paper an investigation for the extent and model type of the downstream network (below 380 kV) is performed. A detailed model for an example downstream network is developed. Different simplifications and equivalent models are compared in frequency domain and in time domain, during cable energization. The impact of the lower voltage network on both the maximum overvoltage and the harmonic content during energization is assessed. Moreover, components that are of major importance are identified and proper equivalent models for the downstream network are proposed. Simulation results show that in particular the type of the 150 kV network (underground cable or overhead line) affects greatly both the maximum overvoltage and the harmonic content during energization. On the other hand, the parameters of end customer loads have only minor effect.

This paper introduces a new DC solid-state circuit breaker (SSCB) concept using a small inductor, which is similar to the inductor used in electro-mechanical breakers. The new SSCB scheme uses the voltage inductor to activate a short circuit protection, in this way the circuit starts to open in the moment of fault condition to prevent the over load current.

This paper proposes a simple circuit configuration and a control strategy of Solid-State Transformer (SST). In the proposed circuit, it is possible to reduce the volume of heat sinks and passive components by using low voltage switching device with low loss characteristic and high frequency operation. Moreover, the circuit employed with the proposed control strategy operates stably even when the ripple voltage is large. Besides, the bidirectional operation of the proposed circuit is also confirmed by simulation. From the simulation result, the capacitance in each cell of the primary side (high voltage side) can be minimized to only 3 µF for 10-kVA system. Moreover, a miniature model with three cells is tested to confirm the fundamental operation of the proposed circuit. As a results, the sinusoidal waveform of the input current is obtained without the large distortion. the total harmonic distortion (THD) of the input current is 2.55%. In addition, it is confirmed that the primary side capacitor voltage of each cell is kept constant without the balance control.

Shifting medium-voltage networks to operate with the neutral grounded via a resistor or an RL circuit is the most promising approach to improving the reliability of electric power supply systems either with or without capacitive current compensating devices. The Smart Grid principles imply minimization of losses to consumers; therefore, the optimal solution for the neutral grounding mode can be reached only with automatically controlled grounding devices. The article is devoted to studying and elaborating algorithms and circuit arrangements for control of the resistor taking into consideration the entire set of conditions and requirements imposed on the characteristics of particular electric networks. The results obtained from simulation of transients triggered by ground faults for a range of initial conditions and network parameters are presented, and the optimal values of active currents, at which an arcing fault unconditionally transfers into a stable mode, are determined. Algorithms are suggested; and circuit arrangements of devices are developed to control the resistor installed in the neutral of compensated and non-compensated networks.

In this paper, we present a low power bump circuit for finding similarity between two voltages. The circuit is based on a voltage correlator that in combination with a differential pair achieves the low power behavior. The circuit has low power consumption and low sensitivity when the different between the two input is large, but as they approach each other the sensitivity increases. The proposed circuit is very simple in design and can have more than 4 orders of magnitude less power consumption than the normal bump circuit.

This paper presents Series-Parallel Topology (SP) of magnetic coupling system for use in Wireless Power Transfer (WPT) applications. Configuration of the system is composed of rectifier circuit, inverter circuit and resonance circuit. Full bridge inverter circuit is powered by rectifier and its output is connected to the LC series resonant circuit. Moreover, the LC parallel circuit with resistance is serve as load of the topology. Electric equivalent circuit model is use to describe PS which yields reflected voltage, primary and secondary current and impedance of the system. The theory of the system is verified using an experimental setup connected to a circular primary coil and secondary coil. Various experiments are conducted for difference distance, arrangement, frequency, angle, and diameter. The analysis compares the efficiency of SP topology and its results are reported.

Stability analysis and measurements are presented for negative capacitance and negative inductance designs of digital non-Foster circuits that include a series resistance and model the effects of latency. Such digital non-Foster circuits provide a new important alternative to analog non-Foster circuits, with potential to address stability and performance issues in important non-Foster application areas such as metamaterials, acoustic cloaking, and electrically-small antennas. The proposed approach includes a resistive component in the signal processing of digital non-Foster RC and RL circuits to help control stability and to mitigate parasitic resistance, and also includes latency effects associated with computation and conversion time. Analysis, simulation, and measured results confirm the desired non-Foster impedances, and show useful regions of stability as a function of resistance and latency.

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Thresholdvoltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

Aiming at the lack of standard design method and the shortcomings of main functions of the existing drive circuit, a “Element-level Design under Transmission Voltage Switch Theory” is set forth and a smallest circuit structure namely as drive-unit, which contains Superstratum-unit, Substratum-unit and LC-unit, is designed in this paper to achieve the necessary functions. The drive circuit of n×n ignition bridges has been got from the structure expansion formula along with the expected life estimation. The Ebers-Moll Model of transistor and the internal circuit of MOSFET were used to make a theoretical analysis and the conclusion of such analysis was verified by simulation subsequently. Actual measurement has been made and the results show that the circuit in simple structure has provided a strong loading ability and accurate output; some elements of the circuit have been heated when the circuit was working; and the response time of the circuit was of the microsecond-level.

A novel technique and related structure for a high-voltage integrated circuit (IC) with totem-pole high-voltage devices are proposed. In this technique, a low control voltage with respect to the tub is used to drive the high-side device in the totem pole through a low-voltage tub circuit, as well as through very small low-side device to drive a low-voltage ground circuit, which in turn drives the low-side device in the totem pole. Therefore, the high-voltage level-shifting circuit can be replaced by the tub circuit which takes only a very small area and has no parasitic effects in comparison with that in the conventional totem-pole high-voltage IC. The structure of low-voltage power supplies for low-voltage ICs is also proposed. The results of numerical simulation verify the applicability of the proposed structure.

This article presents an unequal Gysel power divider (UGPD) based on circuit transformation, which is converted from a Π- to a T-type circuit. The Π-type circuit of a conventional unequal Gysel divider consists of two different value resistors and its connection transmission line. In the proposed T-type circuit, the dummy transmission line and the other transmission line with shunt resistor at center position is connected in parallel. Theoretical analysis was performed to derive the design equations for the proposed circuit conversion. For the validation of the circuit transformation, the UGPD using a T-type circuit at the center frequency of 2 GHz was fabricated and measured. The measured characteristics agreed well with the simulation results. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1529–1531, 2015

This work proposes a fully-digital interface circuit for the measurement of inductive sensors using a low-cost microcontroller (μC) and without any intermediate active circuit. Apart from the μC and the sensor, the circuit just requires an external resistor and a reference inductance so that two RL circuits with a high-pass filter (HPF) topology are formed. The μC appropriately excites such RL circuits in order to measure the discharging time of the voltage across each inductance (i.e. sensing and reference) and then it uses such discharging times to estimate the sensor inductance. Experimental tests using a commercial μC show a non-linearity error (NLE) lower than 0.5%FSS (Full-Scale Span) when measuring inductances from 1 mH to 10 mH, and from 10 mH to 100 mH.

Thin-film magnetic inductors are useful for integrated power delivery solutions for microprocessors and mobile devices. In many of these applications, the inductor dimensions have to be optimized simultaneously with the other circuit components, and thus accurate circuit models are required. Hence, we present an accurate physics-based circuit model that can capture the frequency dependency, losses, and the nonlinear behavior of thin-film magnetic inductors both for the uncoupled and coupled configurations. The model is based on the magnetic circuit description of the inductors with additional elements to model the frequency dependency within the magnetic material. The model is verified using vector network analyzer measurements of direct current biased inductors.

A charge-recycling circuit and system that reuses the energy between two or more stacked CPUs is proposed in order to double the life of a battery. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. Charges are temporarily stored in the tank capacitor and are then reused. To control divided loads, a high-speed and energy-efficient regulator is needed. Internal circuit voltage variation between the upper and lower modules is determined by seven low-drop-out (LDO) regulators, a voltage-boosting capacitor circuit, and the tank capacitor. As a result, stable voltage can be supplied to each CPU, even if the upper and lower loads are different or a battery is being used. The LDOs improve the margin of collection in the tank capacitor or task schedule operation, and power efficiency is raised even further. The circuit can be implemented on silicon without a large external control circuit and inductor such as a switching regulator. This circuit was applied to an in-vehicle lock-step system because the upper and lower loads and tasks are the same. Additionally, by using the proposed task scheduling to maximize efficiency, this circuit can be applied not only to lock-step systems but also to general systems. Test chips were fabricated using 90-nm standard CMOS technology. Although the maximum power efficiency of a conventional circuit with a simple LDO is 44.4%, efficiency of the proposed charge-recycling circuit turned out to be as high as 87.1% with the test chips.

the micro-arc oxidation technology is introduced in this paper firstly. The main circuit is designed according to the design demand. The main circuit is made up by chopper circuit and inverter circuit, the chopper circuit regulates the output voltage. Then the control circuit is designed, the control circuit include the key circuit, A/D converter circuit, driver circuit and LED display circuit.

In this paper, an induction heating system composed of two partly coupled coils connected to a double half-bridge resonant inverter is deeply analyzed. Induction coils are electrically characterized by their electrical equivalents, usually a series RL circuit, where the inductance is determined by the magnetic energy stored in the system and the resistance is associated with the power dissipated in the load, generally, a metallic workpiece. The aim of this work is to obtain the electrical equivalent of an inductor system with two concentric coils used in domestic cookers by means of computational methods, in order to be included into the models used in computational aided electronic tools to simulate the time-domain behavior of the associated electronics. The multiple-coil system is characterized with a frequency-dependent impedance matrix, where the diagonal terms are the impedance of each isolated coil, and the nondiagonal terms are coupling impedance components describing the mutual coupling between coils. The impedance matrix is calculated with finite-element analysis tools, and equivalent passive networks are proposed to perform time-domain simulation with a good accuracy in the frequency range of interest. The proposed system has been experimentally verified, obtaining accurate time-domain waveforms and output power calculation.

This brief analyzes the performance achievable by regularly sampled piecewise constant current waveforms in reducing the peak voltage across the driving terminals of an RC circuit when delivering a given charge over a given time duration into the terminals, as compared with using a fixed current. It is shown analytically for two and three current steps and numerically for more steps that the biggest achievable peak voltage reduction obtained with a simple series RC circuit cannot be exceeded with a more complicated RC circuit. Then the biggest peak voltage reduction that can be obtained is approximately 22.98% using either an infinite number of current steps of infinitesimal duration or a constant voltage drive. These are new basic results on RC circuits and have application to the design of neurostimulators.

This chapter analyzes the first-order passive RC and RL circuits and the second-order passive RLC circuits encountered in all Printed Circuit Boards (PCB). The general understanding of passive circuits in time and frequency domains also establishes a vital background for more complex circuits that contain active elements such as diodes and transistors.

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubb...

SUMMARY This paper presents a low-power sinusoidal supply circuit for our proposed adiabatic logic (2PC2AL). The proposed supply circuit consists of three parts: LC resonant circuit, voltage generator circuit, and peak control circuit. The proposed circuit is simulated using 0.18 μm CMOS technology. The simulation results show that the power dissipation of the proposed voltage generator is 10.8 μW at a 100 nA load, and that of the proposed sinusoidal supply circuit is 35.5 μW at 100 kHz. The power dissipation values of the adiabatic/nonadiabatic 16-bit MPU decoders are also compared. At transition frequencies of 10 kHz to 1 MHz, the proposed decoder with a sinusoidal supply circuit shows a maximum reduction of 75% in power dissipation from to that of a static CMOS.

Approximate analytical solution of linear or nonlinear ordinary differential equations (ODE) can be obtained by Adomian decomposition (ADM) method. The nonlinearities in the ODEs are approximated by Adomian polynomials and a rapidly convergent sequence of approximate functions will be obtained as a solution. The ADM is widely used for numerical simulations of real-world systems in the applied sciences and engineering including nonlinear ODE and DAE problems. Multi-stage Adomian decomposition method (MADM) extends the region of convergence of ADM by integrating over multiple overlapping time intervals. In this paper applicability of the MADM for real-time simulation has been investigated for the first time. 3-term approximation of MADM is used for the solution of a series RL circuit, buck converter and boost converter. Mini-FSS, an indigenous real-time simulator developed under National Mission on Power Electronics Technology (NaMPET) Phase II, government of India, has been used in this paper. The results of the MADM simulation are compared with the Backward Euler method on mini-FSS. The MADM accuracy and the execution times are found to be comparable to the Backward Euler method.

This paper describes the design of a high efficiency energy harvesting circuit combined with antenna. The circuit is composed of a series resonance circuit and boosting rectifier circuit for converting radio frequency power into a DC boosted voltage. For further efficiency improvement, input impedance of antenna is optimized. The simulated output DC voltage is 9.0V for an input of 100mV at 900MHz.

This study proposes a voltage equilibration circuit with a self-oscillation circuit for application to electric double layer capacitors (EDLCs). In typical monitoring circuits, multiple EDLCs are connected in series and the circuits are connected to a power supply. In contrast, the proposed circuits uses a self-oscillation technique, and its voltage is supplied by the EDLC, greatly simplifying the circuit structure. In particular, the circuit comprises only 15 electrical components and self-oscillates without a dead-time control circuit. Moreover, the circuit prevents the flow of the short-circuit current into the drains of the FETs. which causes overcurrent circuit damage. Further, the circuit can be constructed into a module of two serially connected EDLCs. The characteristics and usability of the proposed circuit are evaluated in a simulation and experiment.

This paper presents a process, voltage, and temperature (PVT)-independent constant-gm bias circuit, designed in 0.18µm CMOS technology. In this paper, the conventional precise off-chip resistor is replaced by a MOSFET operating in triode region with a novel bias circuit, which behaves like a PVT-independent resistor. Simulations show that the maximum gm variation across process corners is ±5.2%, and the worst temperature coefficient across temperature range of −40°C to 85°C is ±570ppm/°C. The variation of gm is 1.1%/V across supply voltage range of 1.5V to 2.5V at 27°C. The whole circuit consumes 83µW with supply voltage of 1.8V.

Objective: This paper proposes an electronically tunable active grounded inductor circuit using VDVTA as a new active element. The circuit can replace spiral passive inductors for all Analog Signal Processing and data communications operations. Method/Analysis: The impact of temperature variation on its resonant frequency is investigated using Virtuoso Analog Design Environment of Cadence @ 45-nm CMOS technology node. Findings: This paper carries out a study on CMOS realization of Voltage Differencing Voltage Transconductance Amplifier (VDVTA) and its application as an active grounded inductor. A Bandpass filter circuit is realized using the VDVTA based grounded inductor. Furthermore, the impact of temperature variation on the response of the bandpass filter is analyzed and presented. Novelty/Improvement: The proposed circuit uses only active elements and a grounded capacitor. Due to this, the circuit finds applications in all canonical operations and integrated circuit implementations.

Multi-cell diode-capacitor/inductor based boost derived DC-DC converter provides a simple solution for high step-up voltage regulation in solar and fuel cell generation. However, many passive components increase the order of system model and complexity. Transient modeling analysis reveals that time constant of each component in diode-capacitor/inductor network is much smaller than that of other circuit if the directly charging and discharge processes between capacitor through diode is fast enough. The voltage/current relationship of each capacitor/inductor in multi-cell network is fixed. Multi-cell diode-capacitor/inductor network can be seemed as multi-stage DC transformer. Based on the unique feature, this paper proposes the reduced-order modeling approach for high step-up DC-DC converter with multi-cell diode-capacitor/inductor network. Finally, simulation and experiments verify the correctness and effectiveness of new modeling approach. The unified reduced-order model contributes to better understanding of circuit characteristic and simplification of controller parameters design.

Parallel synchronized switch harvesting on inductor (P-SSHI) circuits have been proved to enhance piezoelectric vibration energy harvesting (PVEH), but the maximum conversion efficiency is obtained only when the voltage across the storage capacitor (VSC) equates to the optimal value. For bi-stable rotating PVEH with nonlinear magnetic force in engineering applications, however, the VSC will change greatly when powering real electric loads, thus it is impossible to maintain high conversion efficiency. In order to solve this problem, this paper presents an improved P-SSHI circuit with controllable optimal voltage (COV-PSSHI) by using a voltage control strategy between the storage capacitor and the electric load. The innovation is to control and maintain the VSC close to the optimal value. Firstly, the COV-PSSHI circuit is proposed and its theoretic model is built in detail. Then its average harvested power (AHP) is theoretically derived and AHP of the COV-PSSHI circuit is proved to be more than that of a classical P-SSHI circuit. In the end, experiments are performed to validate the performance of the COV-PSSHI circuit. It can be seen that the COV-PSSHI circuit can increase the AHP by factor 1.25 compared with classical P-SSHI circuits, which is enough to intermittently power the wireless sensor node. Also power consumption of the voltage control circuit has few effects on the COV-PSSHI circuit. In particular, it needs to optimize the envelop capacitor, the parallel inductor and two threshold voltages of the voltage controller in order to implement the COV-PSSHI circuit well in practice.

Previous design approaches for digital discrete-time non-Foster circuits have typically employed ideal current-output digital-to-analog converters to establish port currents based on measured voltages. In this paper, the design of digital discrete-time non-Foster circuits is presented for the case of voltage-output digital-to-analog converters with finite source impedance. These finite-impedance converters act as Thevenin sources that can be converted to Norton-equivalent sources for design and analysis. However, it is also straightforward to incorporate the finite source impedance directly into the signal processing, and this is the approach presented. In addition, it is often desirable to add series resistance to improve stability or to mitigate parasitic resistance, so the design of series resistor-capacitor and series resistor-inductor digital discrete-time non-Foster circuits are considered. Finally, unavoidable time-delay latencies associated with conversion time and computation time are also included.

The impulse spark-over voltage of the gas discharge tube (GDT) is strongly related to the rate of rise (RoR) of the voltage. At present, due to the convenience of the test instrument, conventional impulse waveforms, such as 1.2/50 and 10/700 μs, are often adopted to conduct such kind of test for GDT. It has been found that these waveforms are able to generate valid waveforms only with limited RoRs and relatively narrow valid voltage ranges. This paper deals with a simple series RC circuit to test the GDT's impulse spark-over voltage using a ramp voltage, which is approached by an initial portion of a steeply rising voltage impulse whose normal peak value is several times the breakdown voltage of the GDT. The basic circuit theory is described, and the RoR of the output voltage is correlated with the circuit parameters. Moreover, the series RC circuit in this paper is found to be able to deliver a ramp voltage with more consistent RoR than an RLC circuit. The results in this paper provide some suggestions for the revision of relevant standards (e.g., ITU-T K.12 and IEC 61643-311). Circuit parameters for different RoRs ranging from 100 V/μs to 1 kV/ns are also established. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

This paper investigates a switching operation when a current source gate drive circuit with energy cycling is used. The current source gate drive circuit consists of a voltage source, an input inductor and switching devices as an H-bridge inverter. The power consumption of the current source gate drive circuit is reduced to compared with that of a conventional voltage source gate drive circuit because the energy of the capacitor between a gate and a source is not consumed in a gate resistance which is not required for the current source gate drive circuit. The switching operation of the proposed current source gate drive circuit in the high frequency inverter is evaluated in experiment. In addition, the power consumption is measured when the switching frequency is changed from 100 kHz to 1 MHz. As a result, it is confirmed that the power consumption of the current source gate drive circuit with energy cycling is reduced by 26% compared with that of the voltage source gate drive circuit at 1 MHz. In addition, the differential configuration of the current source gate drive circuit is considered in order to actualize the regenerating energy. Consequently, the regenerating energy of the inductor and the capacitance between a gate and a source is confirmed on the proposed current source gate drive circuit in simulation.

A single-stage LED is proposed the paper, the LED driver is made of three parts, the first part is a continuous conduction mode (CCM) boost circuit, which make the circuit have a twice voltage gain; the second part is a double tank LLC circuit, which decreases the peak current and improves the efficiency of the system, and here the couple inductor technique is adopted to increase the power density; the third part is the current balancing circuit, which is used to balance the current of different strings. A 35W prototype is proposed in the laboratory to prove the rightness of the analysis, and the efficiency is as high as 95% in the full load state.

This work describes in detail the design, fabrication and characterization of on-silicon coupled inductors. The coupled inductors are fabricated using a double metal layer process for improved performance. Further, the fabricated devices are characterized for small signal, dc bias and large signal testing at high frequencies (up to 15 MHz). The small signal testing includes both impedance analyzer and network analyzer results for inductance, saturation and coupling data on the device. The paper further describes the design and set-up for a large signal testing system allowing for accurate measurement of inductor performance. The parameters are extracted from the ratio between the voltage complex amplitude and the current complex amplitude for sinusoidal excitation. The proposed system is suitable to perform the measurements under different large-signal conditions given by the ac current amplitudes ranging from 0 A to 0.5 A, at frequencies up to 15 MHz. From the impedance analyzer tests, a self-inductance of 50 nH and a dc bias current of 600 mA was measured. From the large signal test, an ac resistance of 1.4 Ω was measured at 15 MHz and ac current amplitude of 0.5 A. The measured data were in line with design parameters.

In this paper, a novel cell voltage equalizer using a series LC resonant converter topology is proposed for a series connection of energy storage devices, namely battery, or supercapacitor cells. The objective of the target project is to design an active voltage equalization circuit that is low cost, small in size and achieves a short voltage equalization time. The target application is electric vehicles. Compared to existing solutions, the series LC resonant converter eliminates the complexity of multi-winding transformers and it can balance series connected energy storage devices quickly by transporting energy successively between the lowest and highest charge cell pairs. The circuit operation and a theoretical analysis is provided. Simulation and experimental results are presented for a circuit balancing three supercapacitors demonstrating from an initial voltage difference of 527 mV to a final difference of 10 mV in 900 seconds.

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.

The nozzle array structure fluidic gyroscope signal compensation circuit was researched. To compensate output voltage signal from the first stage of the gyroscope angular rate sensitive element, which had the perfect linearity and operating temperature range, the signal compensation circuit was designed. Then, the circuit function and principle for each module was analyzed. The signal compensation circuit is composed up Single chip microcomputer, temperature sensor, voltage regulator circuit and peripheral circuit. The experiment results shows that using the signal compensation circuit, the fluidic gyroscope linearity is 1% and operating temperature range is -60°C~+60°C. Therefore, the signal compensation circuit realizes the voltage signal temperature compensation and eliminates noise jamming from the external environment, which provides the foundation for the fluidic gyroscope production and application.