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Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation

Authors :
Woo Young Choi
Hyug Su Kwon
Seung Kyu Kim
Source :
IEEE Electron Device Letters. 38:1317-1320
Publication Year :
2017
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2017.

Abstract

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL circuits satisfying the 1.2-V supply voltage ( ${V}_{\mathsf {DD}}$ ) requirement of the 65-nm technology node. The fabrication process is identical to the conventional 65-nm CMOS baseline process, in which copper NEM memory switches are formed by a dual damascene process.

Details

ISSN :
15580563 and 07413106
Volume :
38
Database :
OpenAIRE
Journal :
IEEE Electron Device Letters
Accession number :
edsair.doi...........9b197d9915c6fb79a43354cd07ee880e
Full Text :
https://doi.org/10.1109/led.2017.2726685