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The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28 nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7 mA/μm which was about 65% larger than that of a simple SCR with the same width of 30 μm and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.

Electrostatic discharge (ESD) devices based on diodes and silicon controlled rectifier for RF I/O protection are evaluated on both ESD and RF performance. Varying from the architecture, layout design and metal interconnection, candidate devices show different parasitic capacitance, ESD efficiency, and turn on speed. Potential solution for further RF I/O application is verified.

In this paper, characteristics of electrostatic discharge (ESD) protection devices operating under ESD stress and various ambient temperatures are investigated. The devices considered are a P +/NW diode and several silicon controlled rectifiers (SCRs) including Lateral SCR (LSCR), Modified Lateral SCR (MLSCR), No Snapback SCR (NS-SCR), Low Voltage Triggering SCR (LVTSCR), and P-Substrate Triggered SCR (PSTSCR) fabricated in a 0.35 μm BCD (Bipolar-CMOS-DMOS) technology. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) tester and the Signatone S1060 heating module, and the TLP I–V characteristics are analyzed in details. TCAD simulation is carried out and underlying physical mechanisms related to the effect of temperature on key ESD parameters are provided.

A novel power-clamp assisted complementary MOSFET (PCACMOS), modified from traditional gate-coupled complementary MOSFET (GCCMOS), is proposed for high robust ESD (Electrostatic discharge) protection application. The power-clamp achieves by RC-NMOS and designs by Spice simulation. The comprehensive performance of the protection schemes are evaluated by the figure of merit (FOM). Compared with traditional gate-coupled MOSFET (GCCMOS) protection scheme, the power-clamp assisted complementary MOSFET (PCACMOS) protection scheme has a similar turn-on speed but higher FOM.

A novel gate-suppression technique derived from source-pumping technique is proposed for Electrostatic Discharge (ESD) protection application. By employing the complementary SCR structure, an improved source-pumping and the gate-suppression scheme are able to extend ESD window and endure a high level of ESD impact without additional layout area cost. The fast rise time TLP test revealed the gate-suppression technique provide more effective protection than the source-pumping technique.

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.

The current saturation behaviors of Dual Direction Silicon Controlled Rectifier (DDSCR) and N+ Modified Dual Direction SCR (NMDDSCR) are investigated under transmission line pulse (TLP) stress, compared with Unidirectional SCR (USCR). DDSCR and NMDDSCR are more prone to saturation current state due to different ESD discharge paths, which are verified by TCAD simulation. The saturation current behavior should be suppressed for better ESD effectiveness and robustness. By increasing the lengths of N+ and P+ diffusion area, the saturation current can be suppressed effectively.

The merged and compact MOS-triggered SCR devices have been compared and investigated in a 0.13 μm CMOS process. From experimental results, the turn-on time of compact MOS-triggered SCR has been improved from ∼7.2 ns of merged MOS-triggered SCR to ∼4 ns. Compared to merged MOS-triggered SCR devices, the compact MOS-triggered SCR devices can achieve a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamping voltage and a higher failure current.

New fully integrated single-chip impulse ultra-wideband (UWB) transmitter front-ends, integrating tunable impulse or monocycle pulse generator with bi-phase shift keying (BPSK) modulator, has been developed using a standard low-cost 0.18-μm CMOS process. The monocycle pulse generator component produces 0.7–0.75 V peak-to-peak monocycle pulse with 140–350 ps tunable pulse duration. The impulse generator generates 0.95–1.05 V peak-to-peak Gaussian-type impulse signal with 100–300 ps tunable pulse duration. The BPSK modulator controls the pulse generator to generate positive or negative pulse signal depending on the “1” or “0” digital data information. The pulse signals produced by the developed transmitters are useful for various UWB applications, especially those requiring the capability of changing ranges and resolutions using only a single system. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1609–1614, 2010; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/mop.25250

A single-chip broadband CMOS receiver front-end, integrating a low-noise amplifier (LNA), a correlator, and a template pulse generator, was investigated in nonsinusoidal time-domain environment for possible use as an impulse-type ultra-wideband (UWB) receiver front-end. Particularly, the CMOS LNA and the multiplier making up the core component of the correlator were designed, fabricated, and tested to verify operation in the UWB range. Time-domain results of the integrated CMOS receiver front-end demonstrate its workability as a receiver for nonsinusoidal UWB applications. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2590–2595, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24682

A novel millimeter-wave cavity resonator, completely compatible with commercial CMOS fabrication techniques, has been designed and fabricated in a 0.25-mum CMOS process and tested. The resonator employs a capacitively loaded cavity topology effectively implemented using the CMOS multimetal-layer and via-hole structure. The CMOS capacitively loaded cavity resonator, including two coupling apertures and microstrip feed lines, occupies an area of 2 mmtimes1.4 mmtimes6.28 mum, which is much smaller than the cavity resonator designed without a capacitive load at the same resonant frequency. It resonates at 30 GHz with a corresponding insertion loss of 2 dB and unloaded quality factor of 22.2. The resonant-frequency reduction is approximately 50%, as compared to that without the capacitive load. The design and performance of a new CMOS coupling aperture, which is useful as a coupling mechanism and a vertical interconnect for highly dense millimeter-wave CMOS RF integrated circuits (RFICs) are also presented. The developed low-loss and compact CMOS cavity resonator can be used to realize various millimeter-wave on-chip passive components such as wideband bandpass filters and diplexers and is suitable for direct integration with other CMOS circuits on a single chip. It is attractive for CMOS RFIC design at millimeter-wave frequencies

A novel low-cost low-power fully integrated tunable transmit module composed of a tunable CMOS monocycle pulse generator and compact uniplanar antenna was designed, built, and tested for ultra-wideband (UWB) impulse systems. The CMOS tunable pulse generator integrates a tuning delay circuit, square-wave generator, impulse-forming circuit, and pulse-shaping circuit in a single chip using a standard low-cost 0.25-mum CMOS process. It can generate a monocycle pulse and Gaussian-type impulse (without the pulse-shaping circuitry) signals with tunable pulse duration. A compact uniplanar UWB antenna was also developed and integrated directly with the CMOS pulse generator chip to form the complete integrated tunable UWB transmit module. Measured results show that the CMOS tunable pulse generator can produce a 0.3-0.6-V peak-to-peak monocycle pulse with 140-350-ps tunable pulse duration and a 0.5-1.3-V peak-to-peak impulse signal with 100-300-ps tunable pulse-duration, and the uniplanar antenna has less than a 18-dB return loss and is suitable for transmitting/receiving UWB time-domain impulse signals covering the entire UWB bandwidth of 3.1-10.6 GHz. Good agreement between measured and calculated performance is also achieved. The UWB transmit module was experimentally characterized and its performance is verified. This UWB module finds applications in various time-domain UWB systems including wireless communications and radar

An improved low-voltage-triggered silicon-controlled rectifier is proposed for on-chip electrostatic discharge (ESD) protection in a 65-nm radio frequency CMOS. The experimental results show that it has a very low intrinsic capacitance of 18 fF at zero bias, a low and tunable trigger voltage in the range of 2.2-4.5 V, a low leakage current of 0.3 nA, and a low overshoot voltage under very fast ESD pulse. It achieves a 1.9-A failure current with only 50×9-μm2 layout area.

Low-voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high holding voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the holding voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the holding voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCR's turn-on characteristic is also discussed.

A novel capacitance coupling complementary dual-direction silicon-controlled rectifier (SCR) (CCCDSCR) for high-voltage electrostatic discharge protection is proposed and verified in 0.5-μm BCD process. The trigger voltage of CCCDSCR can be adjusted by coupling capacitance to meet different protection requirements. Compared with traditional lateral double-diffusion NMOS, LDSCR, stacked field-oxide device, and stacked low-voltage-triggering SCR devices, the CCCDSCR has appropriate low trigger voltage of 27.3 V, high holding voltage of 24.3 V, and highest figure of merit (FOM) according to our defined FOM.

Typical SCR with stripe layout style is modified into segmented one in order to tune the SCR's holding voltage for the ESD protection in different operation voltage domain. SCRs with different segmented style and ratio were made, and according to TLP test results, the most proper one for high voltage ESD protection is selected among them. By delicate layout design and choosing the right segmentation pattern and ratio, the holding voltage of the SCR is obviously lifted to a high level of over 30 V, a high enough value to obtain latch-up immunity.

A new compact, low-cost uniplanar impulse generator using coplanar waveguide structure has been designed, built, and tested. This uniplanar circuit consists of three functions: initial impulse generation, impulse amplification, and impulse compression, which are realized by a step-recovery diode and two-stage GaAs MESFET circuits, respectively. The impulse response has an amplitude of 2.3 V and a half-power pulse width of 115 pS. It has larger amplitude and narrower pulse width than the impulse generated by the SRD circuit alone. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 39: 470–472, 2003

New fully integrated single-chip impulse ultra-wideband (UWB) transmitter front-ends, integrating tunable impulse or monocycle-pulse generator with bi-phase shift-keying (BPSK) modulator, have been developed using a standard low-cost 0.18-µm CMOS process. The monocycle pulse generator component produces 0.7 – 0.75 V peak-to-peak monocycle pulse with 140 – 350 ps tunable pulse duration. The impulse generator generates 0.95 – 1.05 V peak-to-peak Gaussian-type impulse signal with 100 – 300 ps tunable pulse duration. The BPSK modulator controls the pulse generator to generate positive or negative pulse signal depending on the “1” or “0” digital data information. The pulse signals produced by the developed transmitters are useful for various UWB applications, especially those requiring the capability of changing ranges and resolutions using only a single system.

Three types of MOS-triggered SCR structures: Merged MOS-triggered SCR, compact MOS-triggered SCR and boundary-MOS-triggered SCR devices have been fabricated and compared in 0.13µm CMOS process for on-chip ESD protection. TLP testing results show boundary-MOS-triggered SCR structures can achieve adjustable and lower switching voltage, smaller turn-on resistance, faster turn-on speed, the best ESD robustness and sufficient latch-up immunity compared with other MOS-triggered SCRs.

Transmission Line Pulse (TLP) curve of high voltage SCR-LDMOS (SCR embedded in LDMOS) is measured under various repetitious TLP stress to evaluate its Electrostatic Discharge (ESD) protection capability. Results show that trigger voltage has walk-in behavior. TCAD simulation indicates its mechanism involved is explained by a base push-out effect dominated melt filament growth, that turns a robust ESD clamp into a fragile device susceptible to trigger voltage collapse.

A capacitance coupling complementation silicon controlled rectifies (CCCSCR) for electrostatic discharge (ESD) protection application is proposed and verified in 0.5µm BCD process. Compared with traditional complementation silicon controlled rectifies (CSCR), the CCCSCR has a lower trigger voltage. The coupling capacitance, as a tunable trigger of SCR, can meet different protection application demands. And the CCCSCR can fulfill all dual direction ESD stress mode protection, including I/O-VSS, I/O-VDD and VDD-VSS.

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65nm CMOS process. The trigger voltage can be significantly reduced to ㌬3V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5%

A new low-cost, low-power fully integrated CMOS transmitter-antenna was designed, built and tested for UWB systems. The CMOS pulse generator can generate monocycle and impulse signals with tunable pulse duration. The UWB antenna is integrated directly with the CMOS chip. The antenna has less than 18- dB return loss and can transmit and receive UWB impulse signals over the entire UWB bandwidth of 3.1-10.6 GHz. The UWB transmit-antenna module can generate and transmit both monocycle pulses from 140 to 350 ps and impulses from 100 to 300 ps.

There is an error in Fig. 1 in the above-named letter [ibid., vol. 34, no. 8, pp. 1050-1052, Aug. 2013]. The corrected figure is published here.