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In a direct modulation scheme and particularly in portable and wireless sensor network applications, the oscillator limits the transmitter efficiency therefore, the oscillator efficiency is critical and high-efficiency and high-power oscillators are increasingly required. This paper presents a high-efficiency and ultra-low-voltage power oscillator that operates at 2.4 GHz and is implemented in 65 nm CMOS technology. The power oscillator is a self-oscillating class-E power amplifier (PA) that utilizes a positive feedback system. A class-E PA is selected due to its high efficiency. The power oscillator has an optimized power consumption and output power, where a 2.4 mW power consumption is achieved under a 0.4 V power supply. The proposed oscillator demonstrates a maximum output power of $$-0.45$$ dBm and a peak efficiency of 37.5%. The oscillator is tunable between 1.66 and 2.78 GHz. The oscillator is robust to a $$\pm\,15\%$$ frequency deviation from a 2.44 GHz nominal frequency due to process, voltage, temperature variation.

Photo-voltaic (PV) power harvest can have decent efficiency when dealing with high power. When operating with a DC&ndash, DC boost converter during the low-power harvest, its efficiency and output voltage are degraded due to excessive losses in the converter components. The objective of this paper is to present a systematic approach to designing an efficient low-power photo-voltaic harvesting topology with an improved efficiency and output voltage. The proposed topology uses a boost converter with and extra inductor in recycled and synchro-recycled techniques in continuous current mode (CCM). By exploiting the non-linearity of the PV cell, it reduces the power loss and using the current stored in the second inductor, it enhances the output voltage and output power simultaneously. Further, by utilizing the Metal Oxide Silicon Field Effect Transistor&rsquo, s (MOSFET) body diode as a switch, it maintains a minimum hardware, and introduces a negligible impact on the reliability. The test results of the proposed boost converters show that it achieves a decent power and output voltage. Theoretical and experimental results of the proposed topologies with a tested prototype are presented along with a strategy to maximize power and voltage conversion efficiencies and output voltage.

This paper presents an autonomous energy harvester able to perform a high radio frequency (RF) power tracking to achieve a DC renewable power source. The proposed simultaneous triple RF band energy harvesting system has the potential of being deployed along with remote sensor nodes to enhance their operational life-times. Two multi-stages rectifiers harvest the RF energy from three bands: 900 MHz, 1.2 and 2.4 GHz are proposed. A control loop is implemented to reconfigure the operating frequency of the rectifier based on the amount of available input power. The harvester is designed using TSMC 65-nm CMOS technology and tunable matching network to vary the input impedance of the main rectifier between 900 MHz and 1.2 GHz and the second rectifier harvests from 2.4 GHz. The results show a peak efficiency of 57, 43 and 33% at 2.4 GHz, 900 MHz and 1.2 GHz respectively.

Solar power harvesting is one of the most effective ways of providing clean energy. However, the power transfer is a major issue due to the shading effect. Besides; the photo voltaic (PV) output impedance is non-constant and it changes in a nonlinear fashion. This creates a challenge to ensure a maximum power transfer and hence, degrades the efficiency. A recent trend to regulate the efficiency has employed a boost DC- DC converter through adjusting its duty cycle. This paper presents an impedance matrix and analytical study on a single boost converter in continuous current mode (CCM) for low power harvesting application with its limitations to adapt PV’s impedance change. It establishes the relationship between efficiency and output voltage by analyzing the dynamics between load, duty cycle, constantly changing impedance of the PV’s cell and the impact of optimal duty cycle on the efficiency and output voltage as well. It further sheds some light into the over-sensitivity of efficiency with respect to duty cycle. To verify the analysis, an example simulation of 1.4V/17.1mW single boost converter for wearable electronics has been simulated and the result confirms the proposed model and analysis. Furthermore, the paper highlights the trade-off between the efficiency and its impact on the voltage regulation as well.

This paper presents the design and testing results of a complementary metal–oxide–semiconductor double-bulk harmonic-rejection (HR) mixer for wideband applications. An optimal gate-source bias voltage in the sub-threshold regime of the input transistor is found theoretically to achieve maxim HR by analysing the mixing mechanism of double-bulk mixer; and a double-bulk mixer has been designed and fabricated to verify the theoretical analysis. Test results substantiate the existence of the optimal bias point for HR of double-bulk-driven mixer when the sinusoidal local oscillator (LO) is applied. This simple but effective topology can achieve higher than 36, 44, 60 and 62 dB HR ratio for the third-, fifth-, seventh- and ninth-order of LOs, respectively, over broadband. The double-bulk mixer which input bandwidth is from 250 MHz to 3 GHz, including the buffer, consumes 5 mA current from 1 V power supply; the mixer core only consumes 1.5 mA current.

In this paper, the `mixing' mechanism of CMOS bulk-driven (BD) mixer is analyzed in detail. Based on the theoretical analysis, a novel method to improve harmonic mixing rejection (HMR) which is important for wideband mixer is proposed. Three BD mixers of different structures are designed in TSMC 65 nm technology to verify this design methodology. Simulation proves that HMR performance is improved for different mixer structures by following the methodology. The broadband HMR is robust under process, temperature, bias and local oscillator amplitude variation without sacrificing other performances. These proposed mixers offer conversion gain above 4.6, ?0.5 and 11.0 dB, respectively, covering frequency from 850 MHz to 6 GHz. The simulated IIP3 are 14.51, 16.82 and 4.96 dBm respectively. Power consumptions are 0.96, 1.2 and 0.33 mW respectively under 1 V power supply.

This paper presents two low-voltage and low-power CMOS voltage controlled ring oscillators (VCOs) for use in portable wireless sensor applications. The frequency is controlled using an inversion mode MOS voltage controlled capacitor (varactor) to generate a large tuning range between 166 MHz to 600 MHz for the first design and from 250 MHz to 850 MHz for the second one and consume only 151.2 μW and 146.19 μW respectively. The proposed three-stage VCOs are designed and simulated in TSMC 65nm technology. Both operate on a 0.6 V power supply.

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.

A CMOS current mirror (CM) based on the body-driven technique and active feedback scheme is presented. The proposed CM is immune to the threshold voltage limitation and offers much higher accuracy over wider current operating range than other body-driven CMs. The complete analysis of the input-output characteristics, system dc current transfer error, frequency, and noise performance is provided. By using a 1.5V/1V single power supply and 0.18-/spl mu/m n-well process, SPECTRE simulation results validate the analytical results and the overall good performance in terms of wider input-output voltage swing, lower input resistance, and larger output resistance compared with the conventional high-swing cascode CM.

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-μm mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm^2 without the i/o pads

In this paper, we present the design of a CMOS current operational amplifier (COA). A design technique based on current steering is proposed to enhance the frequency capability of the amplifier and achieve higher bandwidth of operation. A complete COA was designed and fabricated using a 1.2-/spl mu/m CMOS technology, the COA occupies an area of 0.13 mm/sup 2/. Results from HSPICE simulations and measurements indicate an open-loop gain of 70 dB, a gain-bandwidth product exceeding 200 MHz, and a settling time of 5.1 ns. The amplifier operated under /spl plusmn/3 V DC voltage supplies, and the power dissipation is approximately 4.5 mW.

This paper presents a novel high efficiency RF to DC converter for RFID applications. The proposed rectifier circuit is designed in 90 nm CMOS technology using single RF source. It exploits an internal Vth cancellation technique along with a leakage current reducer. The circuit performs well in the low input power threshold. The Simulation results at frequency of 920MHz show that the Power Conversion Efficiency (PCE) has improved compared to the conventional rectifier using diode connected transistor and Vth cancellation techniques. The measured PCE is 36.3% at -14.3dBm and is improved to 54.5% with an impedance matching network between the source and rectifiers' input.

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

A novel continuous-time current-mode differentiator with a frequency range extending from DC to 100 MHz is presented. This circuit is constructed using a capacitively coupled current mirror. General first- and second-order circuits, using the differentiator, have also been introduced. To demonstrate how the proposed differentiator can be used to construct higher order filters, a sixth-order band-pass filter with a center frequency at 2.5 MHz and a 1 dB pass-band ripple has been realized and simulated. All simulations were performed using HSPICE for a 1.2 /spl mu/m CMOS process. The total power dissipation for the sixth-order filter is 23 mW from a single 3 V supply.

In this paper, a high-output impedance, wide output swing bulk-driven current source with dynamic biasing is proposed. To increase the output impedance, a bulk-driven gain-boosted cascode feedback amplifier is used. Two dynamic biasing circuits are introduced: one is used to adaptively bias the gate of the current source output transistor while the other is used to supplement current into the output node when the output voltage is low. In addition, the dynamic biasing circuits help to boost the output impedance further. Simulation results show that under 0.6 V supply voltage, the minimum output voltage is below 100 mV and the output impedance is over 200 MΩ.

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm/sup 2/), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF. >

This paper presents an 0.8-V power supply multi-pass loop ring oscillator. The oscillator employs cross-coupled PMOS transistors to improve phase noise characteristic and multi-pass loop to obtain wide frequency tuning range. The coarse and fine controlled signals are also applied to lower the noise sensitivity of the oscillator. Simulations using TSMC 90 nm CMOS technology shows 394MHz to 4.4GHz frequency tuning range and −94.6dBc/Hz at 1MHz offset from 4.4GHz. The power consumption is 11.2mW.

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

A method for the analysis of distributed MOSFET filters is presented. The effects of parasitic capacitances on distributed high-pass MOSFET filters are investigated. Three schemes of MOSFET configurations functioning as distributed high-pass filters are presented and analyzed to demonstrate the method and to illustrate the parasitic effects. The analyses are verified by SPICE simulation and the very high frequency numerical model of a MOSFET given by L.J. Pu and Y. Tsividis (1990). >

This paper presents charge sampling circuit using new high linearity transconductor (Gm) cell that has third order distortion cancellation. The proposed Gm-cell has almost constant transconductance value over ±200mV input voltage range. The charge sampling circuit has SNDR around 73 dB with ENOB of 11bits and it consumes 4.38mW power. Its input referred noise is 15.29nV/√Hz and noise figure is 24.67dB at 81MHz. This architecture is used to implement a programmable analog baseband filter for Bluetooth and UMTS. Simulations were carried out using the TSMC 0.18 µm CMOS technology with supply voltage of 1.6V.

A current mirror circuit that uses body-driven MOSFETs to achieve an ultra-low input and output voltage is presented. High-gain amplifiers, suitable for a deep submicron process, are used to provide matching as well as input and output regulation. Simulation results were verified with measurements performed on a fabricated chip using the 90-nm CMOS process from ST-Microelectronics.

The authors describe the use of a switched-current concept in realizing a winner-take-all circuit for artificial neural networks. Unlike other conventional winner-take-all networks the new approach displays no inhibition between neurons but rather allows the neurons to compete among themselves. Equations governing the operation as well as its limitations are presented and verified through simulations. Control logic is required making this circuit fully compatible with the mixed analog/digital integrated technology. >

Design criteria for tunable matching networks (TMN) are given with emphasis on the MEMS technology in the FM band. An important result is obtained proving that minimal number of components is needed to match a range of loads in the full band. Exact design equations are given rather than approximations based on the Smith Chart. Parasitic effects are also incorporated. Future fully MEMS-based transceivers with automatic antenna tuning units are presented.

This paper presents a low-power CMOS /spl Sigma//spl Delta/ modulator for a single-chip Bluetooth transceiver. It implements a low-power, fast-settling operational amplifier and can achieve 75 dB SNDR and 81 dB dynamic range over 1 MHz bandwidth. The design was fabricated using 0.18 /spl mu/m CMOS process. The chip size is 0.63mm/sup 2/ and the power dissipation is only 64 mW.

A new class-E power amplifier design approach, in which the design problem is posed as combinatory optimization, is described. To incorporate the frequency dependent components in the optimization procedure, a simplified frequency domain simulation method was proposed to speed up the simulation. A 2.4 GHz 85 mW fully differential class-E CMOS power amplifier with 69% power drain efficiency has been designed in a 0.18 /spl mu/m standard digital CMOS process.

A novel high-performance low-voltage CMOS current mirror is proposed. The circuit is based on body-driven CMOS technology and implements gain-enhancement technique. It offers high transfer accuracy over wide current range, extremely high output impedance that makes it suitable for current output stage and ultra low input voltage requirement down to very close to 0 V. Simulation results using 0.18 /spl mu/m N-well CMOS technology confirm the excellent performance of this novel current mirror.

The design of a high-performance CMOS operational-amplifier (op-amp) in 3- mu m double-level-metal technology is presented. The amplifier makes use of stacked (cascode) current source techniques and an enhanced push-pull output stage. This op-amp will be used for the realization of high-frequency switched-capacitor (SC) filters. SPICE simulations of the op-amp show a unity gain bandwidth of 40 MHz and a DC gain of 72 dB when using a bias current of 100 mu A and a load capacitance of 15 pF. A test chip implementing the op-amp and other analog test cells was fabricated. Test results from the fabricated device demonstrate a DC gain of about 67 dB, with a unity gain bandwidth of about 40 MHz and a 36 V/ mu s slew rate when using a bias current of about 100 mu A and a 15-pF load. >

In this paper we present a CMOS front-end amplifier with on chip tuning circuitry. The design is targeted towards applications in wireless RF communications. In the design, integrated inductors are used to provide frequency tuning and impedance matching capabilities. Negative resistance is used to compensate for the losses in these inductors in order to achieve reasonable quality factors. Two amplifiers of the same topology were designed using a 1.5 /spl mu/m p-well process to operate at 900 MHz and 1.9 GHz. Simulation using HSPICE show that quality factors exceeding 20 are possible. The amplifiers provide gains of 23 dB and noise figures of approximately 5 dB.

Presents a single and differential ended 900 MHz RF amplifier based on CMOS technology, The RF amplifiers are designed to take into account the ESD and input pad parasitics. The integrated inductors are all below a value of 10 nH. This is done to reduce the physical size of the inductors and to increase the self-resonating frequency of the inductors.

A new CMOS realization of an operational transconductance amplifier is presented. It is based on the cross-coupled configuration and is biased by the common-mode voltage. The circuit has only two transistors between the supply line and ground which makes it suitable for low-voltage applications. Simulation results show that the circuit is highly linear and tunable over a wide range bias voltage. The circuit is used to realize 2/sup nd/ generation current conveyor (CCII) and differential current conveyor (DCC) that have excellent performance.

The authors present a CMOS integrated bandpass amplifier tuned at 1.9 GHz and suitable for highly integrated RF receivers. Tuning is achieved using on-chip integrated inductors. The amplifier includes quality factor enhancement circuitry to enhance the low Q of these integrated inductors. Simulation using HSPICE indicates a gain exceeding 20 dB with a quality factor of 20.