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A current-fed dual active bridge dc–dc converter using dual transformers is proposed for the energy storage system and electric vehicles, which is suitable to be used in wide input and wide output voltage range bidirectional power flow applications. Optimized switching pattern and the coupling relationship among all the controlled variables have been explored in order to minimize the leakage inductor current peak and rms value in spite of the load and voltage conversion gain variation, which can reduce the current stress in switches and conduction loss. Furthermore, wide ZVS range can be achieved. The preferred optimized working modes and real-time closed-loop implementation by employing the proposed control strategy are given. The ZVS conditions for each switch are discussed in detail. The turns ratio design is also demonstrated. The effectiveness of the proposed method is verified by the experimental results of a 1-kW prototype.

In this letter, we propose an ultralow-power transformer-based V-band receiver front-end using a 65-nm CMOS technology. Forward-body-bias and transformer-based positive-feedback topologies are utilized to enable its operation at a low drain bias of 0.3 V, while still ensuring its gain performance. A resistive ring mixer, with its advantage of zero-dc-power consumption, serves as the frequency down-converter of the system. The proposed receiver front-end demonstrates an 8.5-dB conversion gain and possesses the power-saving ability to use only 0.7 mW of dc-power consumption.

In order to improve the efficiency of battery charging and discharging in a wide conversion gain, a dual-transformer-based full bridge converter using a block capacitor was proposed. By adding the blocking capacitor in the primary side of one transformer, an extended zero voltage switching (ZVS) range is obtained in a wide output voltage range, which is achieved by regulating the secondary voltage of the transformers to match the output voltage according to the voltage-second balance in both boost and buck modes. Besides, a mirror-symmetrical modulation is introduced in reverse power flow to avoid a limited ZVS range of the traditional dual-transformer converter. The power characteristics and ZVS range are analyzed in detailed. The analysis results and transformer current are compared with the published dual-transformer converter and the conventional dual active bridge (DAB) converter to demonstrate the advantages. Finally, a 300W prototype was built and tested to verify the effectiveness of the proposed converter.

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

this paper presents a receiver front-end in 180 nm CMOS operating at 28 GHz. The receiver front-end consists of a low-noise amplifier (LNA) and a mixer. By embedding Quadrature coupler into the mixer, the circuit delivers in-phase and quadrature outputs. The proposed architecture avoids the traditional in-phase/quadrature (I/Q) implementation by quadrature voltage control oscillators (VCOs) with larger power consumption at high frequencies. The adopted transformers and inductors are optimized by a momentum tool. The simulated results show the receiver front-end provides a NF of 5.48 dB, a conversion gain of 18.1 dB, and an IIP3 around −8.5 dBm at 28 GHz. The circuit dissipates 17.3 mW under 1.8 V power supply.

This paper proposes a 20 — 80 GHz RF double-balanced mixer utilizing a hybrid down-conversion scheme. To achieve the down-conversion over the entire range, two mixers are operating in double-down-conversion for fixed IF of 3 GHz and RF is divided into low-band 20—44GHz and high-band 44 — 80GHz. For the low-band, the first mixer is bypassed and the second mixer used for down-conversion. For the high-band, both mixers are used for down-conversion. This results in reducing the LO tuning range by over 50% as compared to a regular sliding IF scheme. The design is evaluated using simulations of the designed mixer in 22nm CMOS technology, achieving a conversion gain of over 5 dB throughout the RF bandwidth, a minimum IIP3 of 4.9 dBm and minimum noise figure of 5.1 dB.

This paper presents an Image Rejection Mixer (IRM) for 5.8 GHz Dedicated Short Range Communication (DSRC) Receiver. The proposed IRM operates with both of the Intermediate Frequencies (IF) equal to 5 MHz and 10 MHz which is suitable for the regions which their standard IF is equal to 5 MHz or 10 MHz. The proposed mixer is implemented with by image rejection function through a passive RC polyphaser filter. The proposed IRM has a conversion gain up to 7.1 dB, an image rejection ratio (IRR) which exceeds 24.4 dB at both of the IFs equal to 5 MHz and 10 MHz, and its output 1-dB compression point and third-order intercept point are −12.3 dBm and −2.9dBm respectively. The proposed mixer is designed in 130 nm CMOS process and its power consumption is $84\ \mu \mathbf{W}$ .

Differential implementation is becoming highly popular in Radio Frequency Integrated Circuit (RFIC) design, notably for its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One RF front-end building block that is usually designed as a differential circuit is the mixer. This paper presents a design, study, and optimization of a differential mixer, more specifically the Gilbert-cell mixer (also known as double-balanced mixer) implemented on a direct-conversion architecture in a standard 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. Operating frequency is set to 5GHz, which is a typical frequency for Worldwide Interoperability for Microwave Access (WiMAX) receiver. Impedance matching was necessary to design and fully optimize the mixer design. The direct-conversion Gilbert-cell mixer design ultimately achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.

A 1–10 GHz, radio frequency (RF) mixer with an active inductor (AI) designed in 0.18 μm Technology has been proposed in the paper. It uses a conventional single-balanced mixer and double-balanced mixer for demonstrating wideband performance without using an inductor. The AI-based single-balanced mixer achieves conversion gain (CG) of 6–3 dB, S11 of -12 dB, and the third-order input intercept point (IIP3) of 0.15-2 dBm. Moreover, the active transformer that is designed based on the proposed AI is used in the Gilbert cell mixer for improving the bandwidth (BW). The proposed AI-based Gilbert cell mixer achieves 4.5-3 dB of CG, and 2.7-3.8 dBm of IIP3. The 3-dB BWs of the proposed mixers are 1–10 GHz.

This paper presents a CMOS mixer with excellent input matching and high conversion gain @ 2.4 GHz. Inductive source degeneration is used for RF port input matching. This mixer utilizes inductive shunt peaking for conversion gain boosting. Active loads having drain-gate AC resistive blocking devices are employed for further enhancement of IF output power. The proposed mixer is designed, simulated and implemented in TSMC 0.18 μm CMOS process. This mixer layout occupies an active area of 0.293 mm2. Its input matching network is tuned to 2.4 GHz. It achieves a conversion gain of 31.88 dB while driving a 3.43 mA from a 1.8V supply. It has a FoM of 13.321.

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°.

This brief presents the design of an improved linear Gilbert mixer with high conversion gain and low noise figure by using multiple gated transistor (MGTR) and switched biasing technique. This mixer operates at a radio frequency (RF) of 2.4GHz with a local oscillator (LO) power of 5dBm in UMC 180nm process. The MGTR method is used to increase the linearity of the proposed mixer by the parallel combination of transconductance stage transistors and auxiliary transistors. The switched biasing technique is adopted for a current source instead of static biasing which lowers the noise figure. The integration of two techniques result in a conversion gain (CG) of 10.9dB and a noise figure (NF) of 7.2dB with the third order input intercept point (IIP3) of 10.79dBm. This proposed mixer circuit consumes 4.2mW power from a supply voltage of 1.8V.

This paper presents an inductorless 60GHz down-conversion mixer integrated in a 22nm FD-SOI CMOS technology. The mixer is based on a single-balanced architecture followed by a common-source output buffer, and it performs a zero-IF conversion with –3dB corner frequency at 1GHz. The maximum differential single-side-band (SSB) conversion gain is 6dB, in agreement with simulation and circuit analysis. The required LO power is –4dBm, while the dissipated power is 18mW. The silicon footprint is 0.05mm2, which to the knowledge of the authors is the smallest reported so far for down-conversion mixers operating at 60GHz, with a factor 3 of improvement.

As a reliable device for voltage regulation and isolation, a line frequency transformer is commonly connected in series with bidirectional converter (BIC) to interlink the ac and dc networks of hybrid ac/dc microgrid. However, it may not be suitable for the applications where weight and space occupation are of important concerns such as hybrid ac/dc microgrid. In this paper, bidirectional resonant dc transformer (BRDT) is proposed to replace the conventional bulky transformer for bus voltage matching and galvanic isolation. In order to simplify systematic coordination with BIC and central controller, BRDT is designed as an ideal transformer with simple open-loop scheme. 50% duty ratio scheme is implemented as it has been proven to be better than the phase-shift scheme in order to ensure BRDT conversion efficiency. A generalized model for various BRDT topologies, including CLLC, CLL, and LLC high frequency transformer (HFT), is established for analysis. The impacts induced by the transformer leakage, magnetizing inductances, and extra resonant capacitors are considered when designing the HFT. The conversion gain of the designed BRDT has also been analyzed in the full power range. Lab-scale prototypes for BRDT and hybrid ac/dc microgrid have been developed for experimental verifications. The performances of BRDT and system in both steady and transient states have been confirmed. This work was supported in part by the National Natural Science Foundation of China under Grant 51507138, in part by the Young Talent fund of University Association for Science and Technology in Shaanxi, China under Grant 20160117, and in part by the China Scholarship Council. Paper no. TSG-00959-2017.

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer. This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process. Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver. Impedance matching was essential to fully optimize the mixer design. The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.

We demonstrated a novel self-oscillating up-conversion mixer with double-conversion structure in order to overcome a high conversion loss of a self-oscillating sub-harmonic up-conversion mixer. The self-oscillating double-conversion mixer consists of a self-oscillating up-conversion mixer and an up-conversion gate mixer, based on two 100 nm pseudomorphic high electron mobility transistors (PHEMTs). The mixer has an operating frequency of 77 GHz due to the double-conversion of self-generated fundamental LO frequency of 38.5 GHz. The mixer exhibits a good conversion gain of 3.87 dB and a phase noise of −92.9 dBc/Hz at 10 MHz offset. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1989–1993, 2016

This letter presents a 15–21 GHz I/Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of −5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies $1.07~mm^{2}$ . The dc power consumption is 61 mW.

This paper proposes a novel high voltage conversion gain DC/DC boost converter for renewable energy applications and systems. The proposed converter utilizes a three-winding coupled inductor. The presented converter benefits from a unique advantage, as the actual turn ratio of the coupled inductor is decreased in the charging state of the coupled inductor. However, while the inductor is discharging, the actual turn ratio is increased. This feature leads to a very high voltage conversion gain. Furthermore, a passive clamp circuit is employed to recover the leakage current of the coupled inductor. The voltage stresses on the semiconductors are also reduced. In addition, the average current of the primary side of the coupled inductor is zero. This will reduce the total energy stored in the passive elements of the converter. The paper analyzes the Continuous Conduction Mode (CCM) and the operation principles of the presented converter are thoroughly derived. A 250 W laboratory hardware prototype is prepared to verify the proper operation of the presented converter. The obtained experimental results validate the feasibility of the presented converter.

Automation of vehicles requires a secure, reliable, and real-time on-chip system. These systems also require very high-speed and compact on-chip analog to digital converters (ADC). The conventional ADC cannot fulfill this requirement. In this paper, we proposed a Darlington pair- and source biasing-based high speed, secure, and reliable voltage to time converter (VTC). It is a compact, high-speed design and gives high conversion gain. The source biasing also helps to increase the input voltage range. The conversion gain of the proposed circuit is 101.43ns/v, which is 52 times greater than the gain achieved by state-of-the-art design. It also shows less effect of process variation and bias temperature instability.

Recent studies have shown that the power consumption of a wake-up receiver can be reduced by using an envelope detector as its first stage. Designing a low power envelope detector is challenging because of stringent requirements such as data rate, operating frequency, conversion gain and sensitivity. This paper describes the design of a 915 MHz envelope detector which uses a combination of active inductors and an input matching circuit to improve its conversion gain. The proposed design consumes 2 $\mu \mathrm{A}$ of bias current, achieves a 37.8 dB of conversion gain, a sensitivity of -60 dBm and a data rate of 200 kb/s in a 0.13 $\mu \mathrm{m}$ CMOS process.

This paper proposes a modified duty phase shift technique for an M-phase extended-duty-ratio (EDR) boost converter to facilitate the inherent current sharing property and reduced voltage stress on the switching devices of the EDR converter over wider operating region. With conventional phase shift of (360/M)° among the operating phases, a reduced voltage stress and inherent current share between the interleaved boost phases is only possible for the operating region of duty ratio given by (M − 1)/M ≤ D ≤ 1, with a minimum gain of M2. However, for a wide range of input-output application with the need of extended range of voltage conversion gain, the converter will operate over broader duty ratio range. With the proposed duty phase shift technique, the advantages of EDR converter of inherent current sharing and reduced voltage stress on the active devices can be restored over wider operating range allowing a minimum gain of 2 M. The method is validated with extensive simulation results from multi-phase EDR boost and experimental results from a 250 W 3-phase EDR boost with GaN-based hardware prototype operating at 200 kHz switching frequency.

This paper describes low-voltage and low-power design of a CMOS RF receiver front-end circuit for MICS applications. The direct-conversion RF receiver is composed of a single-ended cascode LNA, single-to-differential converting gm-stage, quadrature passive mixer with 25% LO duty cycle, and transimpedance amplifier. Extensive circuit simulations show that the receiver has the maximum conversion gain of 45 dB, the input-referred P1dB of −34.8 dBm, and the noise figure of 2.6 dB, while dissipating 1.4 mW from a 1-V supply.

This paper presents a 24 GHz CMOS I/Q mixer for automotive radar applications. The circuit includes an I/Q mixer core, an I/Q imbalance calibration and IF buffers. In this design, a compact and symmetrical design methodology is adopted to reduce the LO feed-through and I/Q imbalance. Moreover, an I/Q calibration technique is implemented for further improving the I/Q balance. According to the measurement results, the mixer with a pre-amplifier achieves a conversion gain of 24 dB, a NF of 7.8 dB, an input P1dB of −20 dBm, a LO-RF isolation of 57.8 dB, and I/Q imbalance less than 2 degree without tuning. Fabricated in a 0.18-μm CMOS process, the mixer occupies a silicon area of 0.5 × 0.79 mm2 and consumes a total dc power of 35 mW.

Two 81-96 GHz frequency triplers, one balanced and one single device, are implemented using a 0.10 μm GaAs pHEMT process. The EM simulation results show that the triplers perform a best conversion gain of -6.8 and -4.7 dB for the balanced and the single device, respectively. The conversion gain of the balanced tripler operating from 81 to 96 GHz is above -9.6 dB at 3dBm input power. The conversion gain of the single device operating from 81 to 96 GHz is above -8 dB at -0.5dBm input power. The fundamental and second harmonic suppression are as high as 30 dB over the whole operating frequency (81-96 GHz) for both circuits.

In this letter, we present a MMIC frequency tripler using 65-nm CMOS technology. The tripler consists of a buffer stage that overdrives tripler devices into non-linear region, maximizing the third harmonic generation. Adopting differential architecture and transformers impedance matching, the tripler needs no explicit passive filter to enhance harmonic rejections. The tripler shows peak conversion gain of 1.3 dB, saturated output power of −2 dBm with −5 dBm input power. The 3-dB bandwidth spans 57–78 GHz with 60 mW dc consumption.

An ultra-low-power (ULP) CMOS full-band (780/868/915/2400 MHz) ZigBee receiver front-end is presented. The front-end consists of a wideband common-gate LNA and an I/Q current-commutating mixer. Current reuse and active trans-conductance (gm ) boosting techniques are utilised in this design. Details on design and optimisation method for the proposed ULP receiver front-end are provided. Measurement results for 180 nm RF CMOS implementation show the front-end has a conversion gain of 25.2 dB at sub-GHz bands and 17.5 dB at 2.4 GHz band. The minimum noise figure at sub-GHz bands is 7.3 dB. The receiver front-end consumes only 0.826 mA from a 1.0 V DC supply and the size of the core circuit is 0.052 mm2.

A 4-state, highly linear, reconfigurable mixer is presented in this paper. The proposed mixer is an essential part of the environment-aware receiver, introduced in this article. A set of switches are used in the LO and IF stages of the mixer to digitally tune the linearity of the mixer in exchange for lower power consumption. Three sets of cross-coupled pairs are utilized in the mixer to dynamically inject the proper current into the mixer and improve the linearity of each state of the mixer. The proposed mixer is designed using a standard 130-nm CMOS process. The mixer delivers 10, 6.2, 1.8, and −2.9 dBm of third-order intercept point (IIP3) while the average NF is 9.3 dB and varies only 1 dB in different states. Conversion gain of the mixer varies within 16.8 to 7.8 dB in 0.5 to 7 GHz. The mixer consumes 2.4 to 9.6 mW from a 1.2V supply.

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

Summary Several new topologies of single-switch non-isolated DC–DC converters with wide conversion gain and reduced semiconductor voltage stress are proposed in this paper. Most of the proposed topologies are derived from the conventional inverse of SEPIC (Zeta) converter. The proposed topologies can operate with larger switch duty cycles compared with the existing single switch topologies, hence, making them well suitable for high step-down voltage conversion applications. With extended duty cycle, the current stress in the active power switch is reduced, leading to a significant improvement of the system losses. Moreover, the active power switch in some of the proposed topologies is utilized much better compared to the conventional Zeta and quadratic-buck converters. The principle of operation, theoretical analysis, and comparison of circuit performances with other step-down converters are discussed regarding voltage and current stress and switch silicon utilization. Finally, simulation and experimental results for a design example of a 50 W/5 V at 42-V input voltage operating at 50 kHz will be provided to evaluate the performance of the proposed converters. Copyright © 2014 John Wiley & Sons, Ltd.

In this paper, a novel compensation technique is proposed to improve the imbalance of a Marchand balun due to the unequal odd- and even-mode phase velocities of the coupled lines. Using this method, the fundamental rejection of the balanced doubler with the Marchand balun can be effectively enhanced. Two single-balanced doublers using the improved Marchand balun are designed, fabricated, and measured to verify the concept in CMOS processes. One doubler for 15–36-GHz possesses $-$ 10-dB conversion gain with the 3-dB bandwidth of 82.4% and the fundamental rejection of 33 dB. The other doubler for 95–150 GHz achieves $-$ 7.9-dB conversion gain with the 3-dB bandwidth of 45% and the fundamental rejection of 30 dB. With the proposed compensation technique, these frequency doublers feature wide bandwidths and high fundamental rejections.

We successfully designed and fabricated a high-conversion-gain 100-GHz photoreceiver integrated with a UTC-PD and a PHEMT amplifier for 92-GHz carrier photonic wireless communication. Then, in a demonstration of 92-GHz carrier, OFDM, 16-QAM photonic wireless communication, we confirmed that high data rate of 11.03-Gbps (bit error rate of 1× 10−3) could be achieved at a low optical input power, without post amplifiers for the photoreceiver. The designs and the results are discussed.

We present an RF amplitude detector with a conversion gain of −3 V/V for RF amplitude range 0 to 0.6 Vp in 65nm CMOS. On-chip self-calibration structure that automatically corrects the variations within the RF detector itself is proposed. Silicon measurement results show the self-calibration structure improves the detection error of the non-calibrated RF amplitude detector to less than 10% at only 0.23mW power consumption.

In this paper, a F-band 90 nm CMOS frequency doubler using active CS-based Gm-boosted technique is proposed. When the Gm-boosted technique is applied to the frequency doubler design, the input driving power reduces due to the boosted input voltage swing. Therefore, the conversion gain can be improved. The proposed frequency doubler exhibits a conversion of −3.3 dB and a fractional bandwidth of 26.5%. At 60-GHz output frequency, the maximum output Psat is higher than 1 dBm with a maximum dc-to-RF conversion efficiency of 3.4% The output frequency is from 49 to 64 GHz with a fractional bandwidth of 26.5%.

This paper presents a 138–170 GHz active frequency doubler implemented in a 0.13 µm SiGe BiCMOS technology with a peak output power of 5.6 dBm and peak power-added efficiency of 7.6%. The doubler achieves a peak conversion gain of 4.9 dB and consumes only 36 mW of DC power at peak drive through the use of a push-push frequency doubling stage optimized for low drive power, along with a low-power output buffer. To the best of our knowledge, this doubler achieves the highest output power, efficiency, and fundamental frequency suppression of all D-band and G-band SiGe HBT frequency doublers to date.

The impact of the emitter polysilicon etching in Tetramethyl Ammonium Hydroxide (TMAH) on the characteristics of high-linearity mixers fabricated with the low-cost Horizontal Current Bipolar Transistor (HCBT) is analyzed. During emitter formation, the thick layer of α-Si is deposited over the whole wafer, which is then etched-back in the TMAH. The emitter thickness depends on the TMAH etching time and impacts the HCBT's electrical characteristics. Active down-converting mixers with open-collector topology based on Gilbert cell are fabricated with two types of HCBTs with different TMAH etching time using the lowest-cost HCBT technology with CMOS n-well region for n-collector. Measurements of mixers' characteristics are done on-wafer by using the multi-contact probes. The mixers achieve maximum IIP3 of 20.2 dBm and conversion gain of 4 dB. Differences in performance characteristics between two mixer types are small indicating that HCBT's circuit performance sensitivity on the emitter thickness variations is relatively small.

A CMOS LNA design and Gilbert double balanced mixer design for indoor wireless application are presented in this paper. The LNA is designed with current reused technology for lowering the dc power consumption, and the current-bleeding approach is adopted in mixer design for boosting its conversion gain, respectively. The Narrow band LNA achieves the gain of 20dB with noise figure of 1.5dB at 787MHz. The power consumption of LNA is 21.793μW. The proposed Gilbert double balanced mixer achieves the conversion gain of 13.365dB with Noise Figure of 2.12db and IIP3 as -2.8634dB for intermediate frequency of 100 KHz to 100MHz.

This paper presents three single balanced down-converting mixer designs in CMOS 65 nm technology. The three designs operate at 95 GHz and reach a maximum conversion gain of 8, 6.9 and 10.2 dB respectively. Due to the use of single balanced topology, the designs occupy a relatively small core area of 0.89×0.51, 0.078×0.14 and 0.053×0.17 mm2 and their DC power consumption is only 26, 29 and 12.4 mW.

This article proposes a double-balanced 60- to 12-GHz down-conversion mixer fabricated in the 90-nm CMOS process. The proposed mixer has a 5.825 dB measured conversion gain and 13–16 dB noise figure. The input P1dB of the mixer is −4.4 dBm and the measured LO-IF, LO-RF, and RF-IF isolations are above 42, 44, and 41.5 dB, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2456–2458, 2014

A lot of demand for parts of millimeter wave band, as would be expected 57~63 GHz band down conversion mixer was designed and fabricated using IHP 0.25 um SiGe process. Designed and fabricated mixer was double balanced type and located reduced 3D balun at RF port and buffer amplifier at outport for suppression LO signal and conversion gain. Fabricated mixer measured conversion gain of 13.8 dB, -17 dBm and 88 mA of current consumption characteristics, respectively.

In this work, a wideband technique has been proposed that improves the IF bandwidth of mixers and a 24-GHz down-conversion mixer employing the proposed technique has been designed and fabricated based on 0.13- RFCMOS technology. The mixer showed the conversion gain of dB from DC to 5.25 GHz IF for a fixed LO frequency of 24 GHz. Measured P-1dB and LO-RF isolation was -8.7 dBm and 21 dB, respectively. The mixer draws DC current of 10.6 mA from 1.3 V supply.

This article presents a V-band down-converting cascode mixer fabricated in the 0.13-μm CMOS process.The mixer utilizes the cascode topology and adds a buffer to avoid loading effects. The V-band mixer exhibits a conversion gain of −1.7 dB, an input 1-dB compression point of −8 dBm at RF of 60 GHz, IF of 5 GHz, and LO power of 0 dBm. The RF-IF isolation is more than 26 dB. The LO-RF isolation is more than 15 dB. In addition to the good agreement between simulation and measurement, the proposed cascode CMOS mixer with a small chip size has a complete measured performance for further 60-GHz receiver RF front-end integration. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1973–1977, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25408

In this study, a fully integrated active Gilbert cell mixer with two Marchand baluns was proposed.The proposed circuit was designed at 12 GHz with bandwidth from 7.5 to 19 GHz and fabricated in a 0.5-μm pHEMT process. In addition, the “current bleeding” technique was also provided in the Gilbert cell mixer to boost the conversion gain. The greatest conversion gain of 4.5 dB can be achieved in the designed circuit under LO input power of −2 dBm. Both RF-IF and LO-IF isolations were better than 30 dB. The third order intercept point input power, IIP3, achieved as high as 2 dBm. The mixer works from 7.5 to 19 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1302–1306, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25174

In this article, 60 GHz MMIC down-conversion mixers for a 60 GHz communication system are designed and fabricated on-chip using a 0.12 μm GaAs PHEMT process technology with an fT of 78 GHz and fmax of 190 GHz.The characteristics of a 60 GHz monolithic cascode mixer with an open stub microstrip line are compared with those of a 60 GHz monolithic cascode mixer without an open stub microstrip line, which are integrated on-chip including matching and bias circuits. The 60 GHz monolithic cascode mixer with an open stub microstrip line measured at RF 60 GHz show a conversion gain of −16 dB, LO to RF isolation of 21.5 dB, and LO to IF isolation of 40.5 dB. Especially in the case of the mixer, the LO to IF isolation characteristic is much better than that of the 60 GHz monolithic cascode mixer without an open stub microstrip line. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1341–1345, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25191

In this paper, a 2.4 GHz low-voltage CMOS double-balanced down-conversion mixer using neutralization technique has been proposed and verified by circuit simulations and measurements. The grounded source structure was used for low-voltage operation. The neutralization technique was used to improve a conversion gain. The proposed mixer is fabricated in CMOS process for a 2.4 GHz wireless receiver. The mixer consumes 1.94 mW and gives conversion gain of 5.66 dB, input IP3 of 0.7 dBm and P1dB of -11.2 dBm at 1.5 V power supply. Measured results for the designed mixer show improved conversion gain of 2.86 dB over conventional mixer of grounded source structure.

A Gilbert micromixer is demonstrated in this paper using GaInP/GaAs HBT technology. By using an on-chip active LO balun, the micromixer with the single-ended RF, LO, and IF ports is suitable for hybrid RF system applications. The port-to-port isolation has its best performance when the LO signal is balanced. The fully matched high-linearity micromixer has the conversion gain of 12 dB, IP1dB of −9 dBm, IIP3 of 1 dBm when fIF(input) = 300 MHz, fLO = 3.5 GHz, and fRF(output) = 3.8 GHz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1918–1921, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23549

This paper presents design issues of a wideband, low power implementation of a frequency doubler (FD) in a commercial 0.18 μm CMOS process. The FD consists of two identical unbalanced source-coupled pairs with different width-to-length (W/L) ratios, whose inputs are connected in parallel and its output is taken single-ended. Amplitude and phase mismatch at the differential input are considered and it is shown that there is minimal effect on the output amplitude of the 2nd harmonic for a 5 dB difference in input amplitude and a 45° difference in phase. Under matched conditions, the implemented frequency doubler can be operated at a supply voltage as low as 1 V, which corresponded to a power consumption of less than 1 mW, has a 3 dB output bandwidth of 4 GHz and a conversion gain of 2.5 dB. At a supply voltage of 1.2 V, the frequency doubler consumed 1.32 mW, has a 3 dB output bandwidth of 3 GHz and a conversion gain of 5 dB. The phase niose degradation is 6 dB in both cases.

In this paper, a coupled-defected ground structure(C-DGS) using negative inductive coupling is proposed and a bandstop filter(BSF) using C-DGS is designed and fabricated. The proposed C-DGS is the closely-located DGS cells for the negative coupling, the negative coupling of ground currents between adjacent DGS cells greatly improves the stopband characteristics. The proposed BSF utilizing the sharp cutoff response of the C-DGS has a -10 dB rejection band from 4 GHz to 11.3 GHz. A maximum attenuation rate is -64.3 dB/GHz in 3 cell structure, -108 dB/GHz in 5 cell structure. The C-DGS BSF shows the improved attenuation rate 3.8 times in 3 cell structure, 2.4 times in 5 cell structure, Also, the C-DGS BSF is reduced to 35.2 % and 40 % of the DGS BSF, respectively, due to the closely-located DGS cells. We fabricated the single gate mixer using C-DGS BSF. The single gate mixer has 6.6 dB conversion gain.

A fully integrated solution for rejecting the interference caused by wireless local area network transmissions in the 4.9-5.825-GHz band for ultra-wide-band (UWB) receivers is presented. Front-end prototypes implemented in a low cost 0.35-m SiGe BiCMOS technology are used as a test vehicle to assess the effectiveness of the presented approach. The proposed blocker filtering technique mitigates the gain desensitization, third-order intermodulation distortion and second-order intermodulation distortion by as much as 9.8, 7.9, and 6 dB, respectively. At a power consumption of only 49.2 mW, the receiver conversion gain ranges from 22-19 dB while the double side-band measured at the PCB connectors ranges from 5.5-8 dB in the 3.6-7.4-GHz frequency range.