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It is highly desirable to monolithically integrate a high-performance freewheeling diode (FWD) in both Si and SiC power MOSFETs for power electronic applications. This is especially true for a SiC MOSFET since its inherent body diode has a very large turn-on knee voltage (~2.7 V). The purpose of this numerical study is to investigate a new 1200 V SiC MOSFET structure with an integrated heterojunction diode formed between n-type polysilicon and n-type SiC (termed HJD-MOSFET). The proposed HJD-MOSFET uses a mesa structure to accommodate the heterojunction FWD without sacrificing any active area while leaving the split-gate planar MOSFET cells in the trench. A p-shield region surrounding the heterojunction, along with the p-base of the MOS cells, shields high electric fields and maintains a high breakdown voltage. Three key HJD-MOSFET device parameters are identified and optimized in this article. The HJD-MOSFET offers a turn-on knee voltage of 0.5 V, roughly five times lower than the intrinsic SiC body diode or two times lower than a typical SiC Schottky barrier diode due to the low barrier height of the n/n heterojunction (~0.68 eV). Finally, the gate charge of HJD-MOSFET is reduced by 42% compared with conventional MOSFET since the poly-Si gate electrode is significantly reduced to accommodate the heterojunction FWD.

The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this article, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2-kW power factor correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional dc power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in a PFC converter. Online monitoring results show that the ON-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in ON-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain–source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation, and $C$ – $V$ measurement indicate that the main degradation mechanism is hot holes accumulation within the gate oxide above the JFET region and channel region due to high electric field stress.

In this article, the influence of gate loop inductance on the insulated-gate bipolar transistor (IGBT) junction temperature monitoring based on the transient peak gate current temperature-sensitive electrical parameter (TSEP) methods is investigated using the time-domain analysis, SPICE simulation, and experimental work. It is observed that the peak gate current decreases considerably with increasing gate loop inductance, which was not addressed by a previous work. An improved junction temperature estimation model is developed to address this issue and is experimentally validated over a wide range of gate loop inductances. Unlike the previously reported model calibrated for a fixed gate loop inductance, the new model can provide accurate junction temperature monitoring in any power converter based on the same IGBT with a wide range of gate loop inductance values. An error of less than 6.2 °C in IGBT junction temperature estimation is demonstrated even when the gate loop inductance varies by 247%.

The online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This article provides a potential approach for the junction temperature estimation of SiC MOSFET s based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFET s is approximately 5.2 mV/°C and 19.6 mV/°C, respectively.

The extremely high dv/dt of 4H-SiC insulated gate bipolar transistor (IGBT) becomes the major concern in its next-generation large-volume power conversion applications because severe electromagnetic interference (EMI) is induced. However, the root reason for its high dv/dt and the method of suppressing EMI have not been extensively investigated yet. In this paper, we proposed a novel physical model for SiC IGBT to identify the major limiting device design parameters of dv/dt during switching transients. The influences of SiC IGBT’s design parameters on its dv/dt and power dissipation are quantitatively analyzed by means of the physical model. Comparisons between the theoretical predictions and technology computer-aided design simulation results validate the physical model. The results on design optimization of a 18 kV n-channel SiC IGBT shows that 80% reduction of dv/dt and 60% reduction in turn-off power dissipation are achieved simultaneously without sacrificing its forward voltage drop.