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Three basic translinear circuit topologies are modified for use at low supply voltage. They are: (1) the balanced translinear loop; (2) the alternating translinear loop; and (3) the instantaneous-companding integrator. The key to this work is the constructive use of nonsaturated MOS transistors operating in weak inversion. This provides two improvements. First, circuit operation is extended to low supply voltage. Second, accurate realization is enabled since the circuits become immune to MOS body-effect. The proposed techniques are suitable for static and dynamic analog signal processing circuits in mixed-signal chips fabricated in digital CMOS technology and operating at the minimum possible supply voltage.

A gain-enhancement technique based on active bootstrapping is proposed which ideally increases the low-frequency gain by two gain stages with no speed penalty and without adding to the phase shift. Therefore, high-frequency performance and feedback stability are not compromised. In practice, the gain enhancement will be limited by nonidealities. The technique is particularly suited for minimum supply voltages since no cascodes are used and, although the discussion pertains to CMOS, can also be applied in bipolar and BiCMOS technologies. A complete analysis, including the effects of nonidealities, is performed. A generally applicable design methodology is formulated.

It is shown that a generalized interpretation of the translinear (TL) principle leads quite naturally to an extension to MOS circuits. It is shown that two distinct classes of TL circuits exist, one suitable for bipolar and the other for MOS implementation. The MOS-translinear (MTL) circuit principle is derived and an initial classification of simple MTL circuits is proposed. Some examples are given of MTL circuits synthesizing nonlinear functions. >

A novel current-mode analogue multiplier-divider based on the quadratic-translinear principle is presented. The input and output signals are all in current-mode. The circuit has favourable precision, wide dynamic range and is insensitive to variations in temperature and processing. It is suitable for VLSI implementation and can be used in many hardware design fields such as fuzzy logic controllers and analogue neural networks.

A new companding current-mode (CI) integrator principle is proposed. The integrator function is linear despite being composed of nonlinear parts. Its application promises monolithic filters with improved noise performance suitable for low supply voltages. A class AB circuit implementation is proposed which features an extended dynamic range.

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method for computer simulation is discussed.

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

A circuit configuration is presented for wideband analog computation of both the vector-sum function and the RMS-DC conversion function. Design of the circuit is based on a systematic approach to translinear circuit synthesis. Errors due to finite transistor current gain are compensated by means of a novel technique. Measured performance results based on an experimental monolithic implementation in a standard bipolar process are presented. Bandwidths of 25 and 80 MHz are achieved for vector summation and RMS-DC conversion, respectively.

The translinear principle, which is useful in the design of analog integrated circuits, can also be applied to the design of digital integrated circuits. As an example of this technique, a new nonsaturating bistable element is described, which operates according to the translinear principle and which is realizable with standard bipolar integrated circuit processes. The circuit can operate over a wide range of supply current from some milliamperes down to below 1 nA.

Two MOS current gain cells are proposed that provide linear amplification of currents supplied by several linear MOS V-I converters. The gain is electronically variable by a voltage or a current and can be made insensitive to temperature and IC processing. The gain cells have a constant (gain-independent) bandwidth. >

A simple CMOS circuit is reported for generating supply-independent bias voltages and currents, down to a minimum supply voltage. The circuit is compatible with digital processes. Supply interference is rejected by >40 dB for all frequencies.

The authors propose a new linear CMOS transconductor circuit. It has a transconductance linearly variable by a gate voltage and a rather high bandwidth. Moreover, this bandwidth remains constant when the transconductance is varied. The circuit exploits the square-law characteristic of MOS transistors biased in saturation.< >

Multivalued storage elements are of interest in the quest for higher information density of monolithic memories. The optimal radix to be used is a compromise between information content and cost factors such as silicon-chip area. Formulas are developed which enable the optimal radix to be found. Some recently proposed multivalued storage elements are evaluated for optimal radix by means of the derived formulas.

A simplified method of deriving stability criteria for nonlinear circuits is introduced. Unlike the conventional approach which requires construction of a small-signal equivalent circuit and identification of loops, only the basic nonlinear circuit equations are needed. The method is applied to the calculation of the worst-case static noise margin of I2L, which is shown to be much smaller than a recently published result.