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1. Distance-Aware Relay Selection in an Energy-Efficient Discovery Protocol for 5G D2D Communication

Author

Nadège Varsier, Cesar Vargas Anamuro, Jean Schwoerer, Xavier Lagrange, Advanced technologies for operated networks (ADOPNET), Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-RÉSEAUX, TÉLÉCOMMUNICATION ET SERVICES (IRISA-D2), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-CentraleSupélec, Orange Labs [Meylan], Orange Labs, Département Systèmes Réseaux, Cybersécurité et Droit du numérique (IMT Atlantique - SRCD), IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), This paper is part of and thereby supported by the Horizon 2020 project ONE5G (ICT-760809) receiving funds from the European Union., European Project: ICT-760809,ONE5G(2017), Université de Rennes (UR)-IMT Atlantique (IMT Atlantique), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and IMT Atlantique (IMT Atlantique)

Subjects
Computer science, stochastic geometry, 02 engineering and technology, law.invention, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-MC]Computer Science [cs]/Mobile Computing, Base station, Relay, law, Telecommunications link, 0202 electrical engineering, electronic engineering, information engineering, Path loss, Electrical and Electronic Engineering, business.industry, Applied Mathematics, energy-efficient, 020206 networking & telecommunications, Energy consumption, relay selection, Computer Science Applications, User equipment, D2D relaying, Cellular network, mMTC, business, Efficient energy use, Computer network
Abstract

International audience; Massive machine-type communications (mMTC) is one of the main services delivered by the fifth Generation (5G) mobile network. The traditional cellular architecture where all devices connect to the base station is not energy efficient. For this reason, the use of device-to-device (D2D) communications is considered to reduce the energy consumption of mMTC devices. The main idea is to use nearby user equipment (UE) as a relay and establish with it D2D communication. However, the relay selection process also consumes energy, and this consumption can be significant compared to the energy consumed during the data transmission phase. In this paper, we propose a distributed energy-efficient D2D relaying mechanism for mMTC applications. This mechanism favors the selection of the UEs with low path loss with the mMTC device. Through mathematical analysis and simulations, we show that our mechanism allows a reduction of the total energy consumption of mMTC devices (up to 75% compared to direct transmission) when they have an unfavorable link budget. Moreover, our mechanism achieves almost constant energy consumption for a large range of UE densities and distances between the mMTC device and the base station.

Published
2021

2. Scalable Modeling of Transient Self-Heating of GaN High-Electron-Mobility Transistors Based on Experimental Measurements

Author

Ali Soltani, Meriem Bouchilaoun, Samuel Graham, Georges Pavlidis, Hassan Maher, Christophe Rodriguez, Adrien Cutivet, Bilal Hassan, Francois Boone, Laboratoire Nanotechnologies Nanosystèmes (LN2 ), Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Sherbrooke (UdeS)-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Centre National de la Recherche Scientifique (CNRS), Institut Interdisciplinaire d'Innovation Technologique [Sherbrooke] (3IT), Université de Sherbrooke (UdeS), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Puissance - IEMN (PUISSANCE - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), OMMIC, Université de Sherbrooke (UdeS)-École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Optoélectronique - IEMN (OPTO - IEMN), and This work was supported in part by the Fonds quèbècois de la recherche sur la nature et les technologies (FRQNT) and in part by the Natural Sciences and Engineering Research Council of Canada (NSERC). The review of this paper was arranged by Editor R. Venkatasubramanian

Subjects
Materials science, Thermal resistance, Gallium nitride, High-electron-mobility transistor, 01 natural sciences, Temperature measurement, law.invention, [SPI]Engineering Sciences [physics], chemistry.chemical_compound, gate resistance thermometry (GRT), law, 0103 physical sciences, Thermal, Electrical and Electronic Engineering, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, high-electron-mobilitytransistors (HEMTs), business.industry, Transistor, modeling, Electronic, Optical and Magnetic Materials, chemistry, Gallium nitride (GaN), Logic gate, Optoelectronics, thermoreflectance, Transient (oscillation), business, transient temperature measurement
Abstract

International audience; Abstract:This paper details an extraction procedure to fully model the transient self-heating of transistors from a GaN HEMT technology. Frequency-resolved gate resistance thermometry (f-GRT) is used to extract the thermal impedance of HEMTs with various gate widths. A fully scalable analytical model is developed from the experimental results. In the second stage, transient thermoreflectance imaging (TTI) is used to bring deeper insights into the HEMTs' temperature distribution by individually extracting the transient self-heating of each finger. TTI results are further used to successfully validate the f-GRT results and the modeling of the thermal impedance. Overall, f-GRT is demonstrated to be a fast and robust method for characterizing the transient thermal characteristics of a GaN HEMT. For the first time to the authors' knowledge, a scalable model of the thermal impedance is extracted fully from experimental results.

Published
2019

3. Analysis and design of low power SRAM cell using independent gate FinFET

Author

Shyam Akashe, Saurabh Khandelwal, Vandna Sikarwar, and The Endeavour in this paper was supported by ITM University (Gwalior, India) with the collaboration of Cadence System Design (Bangalore, India).

Subjects
Hardware_MEMORYSTRUCTURES, Materials science, business.industry, Sram cell, Transistor, Electrical engineering, Short-channel effect, Hardware_PERFORMANCEANDRELIABILITY, law.invention, CMOS, law, MOSFET, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, FinFET, SRAM, Static random-access memory, Electrical and Electronic Engineering, business, Standby power, Hardware_LOGICDESIGN, Leakage (electronics)
Abstract

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

Published
2013

4. Development of 3T eDRAM gain cells for enhancing read margin and data retention

Author

Shyam Akashe, Saurabh Khandelwal, Tarushree Varshney, and This paper was supported by ITM (Gwalior) with the collaboration of Cadence System Design (Bangalore, India).

Subjects
Very-large-scale integration, Engineering, Dynamic random-access memory, business.industry, 020208 electrical & electronic engineering, Transistor, Electrical engineering, 02 engineering and technology, eDRAM, 01 natural sciences, PMOS logic, law.invention, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, logic compatible eDRAM, data retention, 3T gain cell, enhanced read margin, static power, nanotechnology, Electrical and Electronic Engineering, Data retention, 010306 general physics, business, Dram, NMOS logic
Abstract

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz1/2.

Published
2016