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Degradation mechanism of stacked high-k gate dielectrics has been studied with metal-oxide-semiconductor capacitors having HfAlOX/SiO2 films of various thickness combinations. A large leakage current with a peaked shape, named as the low-voltage peak current (LVPC), has been observed in the low-voltage region even in the initial current–voltage characteristics. It has been shown that a main part of LVPC is the transient current component controlled by the process of hole injection to traps in the vicinity of the HfAlOX/SiO2 interface through the interfacial SiO2 layer. By the electrical stress, both the transient and the steady-state current components monotonically increase with time having different rates. Steady-state component has significantly larger rate than the transient component, and the same rate with the stress-induced leakage current (SILC) observed in the high-voltage region, indicating that the steady-state component of LVPC should be regarded as the SILC in the higher-voltage region extending down to the lower gate voltage region where the LVPC is observed. [ABSTRACT FROM AUTHOR]

Dielectric breakdown mechanism of gate dielectrics has been reconsidered with SiO2 films of various thicknesses ranging from 3.6 to 9.5 nm. Careful time-dependent dielectric breakdown (TDDB) measurements have realized the detection of anomalous lifetime (TBD) lowering than the expectation from generally accepted power-law (PL) model at relatively low-voltage region in 6- and 6.5-nm-thick films. Analysis from the viewpoint of the hole and electron fluence to breakdown (QBD,hole and QBD,el) has demonstrated the dominant carrier change(DCC) from hole to electron with the lowering of the stress voltage. These results strongly support the DCC model. The DCC model provides stress voltage-independent defect generation efficiencies of electron and of hole at the stress voltage region where each carrier dominates the breakdown, while the PL model provides the stress voltage-dependent efficiency. The DCC model is also capable to explain the empirically reported linear electric field (E) dependence of TBD in a wide range of stress voltage which supports the thermochemical model (E-model). Therefore, it is expected that the DCC model can also be employed in the lifetime prediction of gate dielectrics thicker than ~5 nm, where the E-model is generally employed in the lifetime insurance of actual market products. The DCC model is expected to give longer predicted TDDB lifetimes at the actual device operating conditions in most devices than the E-model and other models and, hence, more aggressive usage of gate dielectric films can be realized. [ABSTRACT FROM AUTHOR]

Anomalous Time Dependent Dielectric Breakdown (TDDB) statistics of thick gate dielectrics, i.e., too large stress field/voltage dependence and nonlinear Weibull plot of TDDB lifetime, have been observed. Through the analysis of behaviors under the TDDB stress and also the comparison with thin gate dielectrics, it has been revealed that just the intrinsic charging of injected carriers to initial and stress-generated defects induces the dynamic stress relaxation under the constant–voltage stress, resulting in anomalous TDDB statistics. This charging-induced dynamic stress relaxation (CiDSR) effect reduces the validity of well-known Weibull statistics and prevents us from accurately predicting TDDB lifetimes utilizing various conventional scaling procedures, such as area, failure rate, and temperature scaling. Impact of the CiDSR effect increases with the thickness of gate dielectrics and the development of an appropriate lifetime prediction method is urgent not only for Si devices but also for various compound devices having thick gate dielectrics, such as GaN and SiC power devices. [ABSTRACT FROM PUBLISHER]

Degradation behavior of oxide–nitride–oxide (ONO) stacked gate dielectrics used in metal–oxide–nitride–oxide–silicon (MONOS)-based flash memories has been studied. Occurrence of the soft breakdown (SBD), which is well known in single-layer ultrathin silicon dioxides, has been revealed even in these thick and stacked dielectrics. The SBD of ONO dielectrics shows similar characteristics with that of silicon dioxides in locality, current/voltage fluctuation, and the dependencies of the ratio of SBD on the gate area and stress condition. These findings require the countermeasure for SBD even in MONOS-based flash memories and also give useful information on the reliability of high-k stacked gate dielectrics. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: The carrier conduction and the degradation mechanism in n+gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO X (Hf: 60at.%, Al: 40at.%)/SiO2 dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150°C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO2 layer (IL) thickness increases in a fixed high-k layer thickness (T high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO2/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3nm, the hole current is dominant in the leakage current, regardless of T high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n+poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n+poly-Si gate. Both the defect generation rate and the defect size in the HfAlO X /SiO2 stacks are large compared with those in SiO2. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO2 could be related to a larger dielectric constant of the high-k layer. [Copyright &y& Elsevier]