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To measure the micro-displacement reliably with high precision, a single-ended eddy current sensor based on temperature compensation was studied in detail. At first, the principle of the eddy current sensor was introduced, and the manufacturing method of the probe was given. The overall design plan for the processing circuit was induced by analyzing the characteristics of the probe output signal. The variation in the probe output signal was converted to pulses with different widths, and then it was introduced to the digital phase discriminator along with a reference signal. The output from the digital phase discriminator was processed by a low-pass filter to obtain the DC component. At last, the signal was amplified and compensated to reduce the influence of temperature. The selection criteria of the frequency of the exciting signal and the design of the signal conditioning circuit were described in detail, as well as the design of the temperature-compensating circuit based on the digital potentiometer with an embedded temperature sensor. Finally, an experimental setup was constructed to test the sensor, and the results were given. The results show that nonlinearity exists in the single-ended eddy current sensor with a large range. When the range is 500 μm, the resolution can reach 46 nm, and the repeatability error is ±0.70% FR. Within the temperature range from +2 °C to +58 °C, the voltage fluctuation in the sensor is reduced to 44 mV after temperature compensation compared to the value of 586 mV before compensation. The proposed plan is verified to be feasible, and the measuring range, precision, and target material should be considered in real-world applications. [ABSTRACT FROM AUTHOR]

The Simons Observatory (SO) is a cosmic microwave background instrumentation suite being deployed in the Atacama Desert in northern Chile. The telescopes within SO use three types of dichroic transition-edge sensor (TES) detector arrays, with the 90 and 150 GHz Mid-Frequency (MF) arrays containing 65% of the approximately 68,000 detectors in the first phase of SO. All of the 26 required MF detector arrays have now been fabricated, packaged into detector modules, and tested in laboratory cryostats. Across all modules, we find an average operable detector yield of 84% and median saturation powers of (2.8, 8.0) pW with interquartile ranges of (1, 2) pW at (90, 150) GHz, respectively, falling within their targeted ranges. We measure TES normal resistances and superconducting transition temperatures on each detector wafer to be uniform within 3%, with overall central values of 7.5 m Ω and 165 mK, respectively. Results on time constants, optical efficiency, and noise performance are also presented and are consistent with achieving instrument sensitivity forecasts. [ABSTRACT FROM AUTHOR]

The quantum critical detector (QCD), recently introduced for weak signal amplification [L.-P. Yang and Z. Jacob, Opt. Express 27, 10482 (2019)], functions by exploiting high sensitivity near the phase transition point of first-order quantum phase transitions (QPTs). We contrast the behavior of the first-order and the second-order quantum phase transitions in the detector. We find that the giant sensitivity, which can be utilized for quantum amplification, only exists in the first-order QPTs. We define two new magnetic order parameters to quantitatively characterize the first-order QPT of the interacting spins in the detector. We also introduce the Husimi Q -functions as a powerful tool to show the fundamental change in the ground-state wave function of the detector during the QPTs, especially the intrinsic dynamical change within the detector during a quantum critical amplification. We explicitly show the high figures of merit of the QCD via the quantum gain and the signal-to-quantum noise ratio. Specifically, we predict the existence of a universal first-order QPT in the interacting-spin system resulting from two competing ferromagnetic orders. Our results motivate new designs of weak signal detectors by engineering first-order QPTs, which are of fundamental significance in the search for new particles, quantum metrology, and information science. [ABSTRACT FROM AUTHOR]

Sensorless drives of interior permanent magnet synchronous motors (IPMSMs) find a broad range of applications due to their inherent benefits. In practical electrified propulsions, the IPMSM drives are usually working in highly utilized conditions where the performance and stability could deteriorate. Without considerable compensation, this vulnerability causes the existing phase-locked loops (PLLs), estimators, or observers to lose the synchronization with the rotor position. To achieve better performance and reduce the estimation error, in a PLL-type framework for sensorless control, a position error observer (PEO) utilizing the current errors as correction terms plays the role of the phase detector. A reduced-order extended state observer (ESO) is presented to form the loop filter with a switched nonsmooth feedback structure. The outstanding property of the PEO and nonsmooth ESO is verified through experiments. The results demonstrate its strong adaptability for model uncertainties and disturbances along with the quick convergence speed and minimal oscillation. [ABSTRACT FROM AUTHOR]

This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller–Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases and calculating optimal weights, the SPD exhibits optimized phase-locking characteristic that maximizes the PAM-4 vertical eye opening (VEO) compared with the conventional logical approaches. In addition, unlike SS-MMPD, which may suffer from a severe multiple-locking problem, the SPD tracks a unique and optimal sampling phase even with an adaptive decision-feedback equalizer (DFE). For verification, a prototype PAM-4 receiver is fabricated in 40-nm CMOS technology and occupies 0.24 mm2. Tested with PRBS-7 patterns, it achieves a bit error rate (BER) of less than $10^{-11}$ and energy efficiency of 2.4 pJ/b at 48 Gb/s. [ABSTRACT FROM AUTHOR]

The demand for low-power wireline circuits has motivated extensive work on novel circuit solutions. This article describes a one-eighth-rate clock and data recovery (CDR) circuit and a demultiplexer (DMUX) for processing four-level pulse-amplitude modulation (PAM4) signals in receivers (RXs). Detecting both major and minor data transitions, the proposed architecture can achieve a wider loop bandwidth (BW), suppressing oscillator phase noise and improving the jitter tolerance. Fabricated in 28-nm CMOS technology, the prototype provides a jitter transfer BW of 160 MHz with a tolerance of 1 UI at 10 MHz. [ABSTRACT FROM AUTHOR]

This work presents an ultra-low jitter, direct $W$ -band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this $W$ -band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the $W$ -band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm2. The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoMJIT of–248.2 dB, which is the best among the state-of-the-art $W$ -band frequency synthesizers. [ABSTRACT FROM AUTHOR]

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance of QT1-PLL deteriorates in the presence of an off-nominal frequency unbalanced grid voltage component. Moreover, the sensitivity towards the fundamental frequency negative sequence (FFNS) component is high. Hence, this paper proposes a novel enhanced QT1-PLL solution that is insensitive to unbalance in the grid voltage signal during off-nominal frequency conditions. The proposed adaptive phase detector makes it possible to estimate both the fundamental frequency positive sequence (FFPS) and FFNS components with a high degree of immunity against harmonics. Notably, the pre-loop separation of the FFPS and the FFNS components helps suppress the second harmonic oscillations for improving the parameter estimation accuracy. The loop-filter design of QT1-PLL remains unaffected and requires a proportional gain to estimate the fundamental phase and frequency information. To address the DC offset issue, a modified delayed signal cancellation method is also proposed, which can theoretically eliminate the DC offset for any arbitrary delay length. A small-signal model of the proposed PLL is developed for the sake of stability analysis. Comparative numerical simulation and experimental results are provided with various variants of QT1-PLLs to demonstrate the performance improvement achieved with the proposed technique. [ABSTRACT FROM AUTHOR]

This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm2 and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively. [ABSTRACT FROM AUTHOR]

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. [ABSTRACT FROM AUTHOR]

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance. Besides, a novel frequency locking method is presented, which provides fast lock and seamless hand-off to main PLL operation. The PLL has been fabricated in a 28-nm CMOS technology process, and it synthesizes frequencies from 11.9 to 14.1 GHz, achieving an rms jitter of 58.2 and 51.7 fs (integrated into the 1 kHz–100 MHz bandwidth) for a fractional-N and integer-N channel, respectively. The reference spur is as low as −73.5 dBc, while the worst case near-integer fractional spurs are lower than −63.2 dBc. With a power consumption of 18 mW, the jitter-power figure of merit is −252.1 dB (fractional-N) and −253.3 dB (integer-N). The locking time is below 9 $\mu \text{s}$ for a 1-GHz frequency step. The synthesizer occupies 0.16 mm2, including decoupling capacitors. [ABSTRACT FROM AUTHOR]

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than $11 \mu \text{s}$. The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10−12 and energy efficiency of 0.96 pJ/b. [ABSTRACT FROM AUTHOR]

This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/ $\mu \text{s}$ ] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- $\mu \text{W}$ RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW. [ABSTRACT FROM AUTHOR]

Coherent processing in cooperative multi-agent networks can achieve significant performance gain via accurate alignment of observed signals. However, the inaccessibility of phase information in mobile scenes prevents the acquisition of a high degree of coherence for target detection. This paper presents a quasi-coherent mobile detection framework for cooperative multi-agent networks, which exploits the phase information inherent in the carrier wave of direct-path signals. Specifically, we derive the quasi-coherent detector with the aid of phase calibration by incorporating the maximum likelihood estimation of phase-related parameters obtained from direct-path signals. Next, we characterize the detection performance degradation induced by the mismatch of initial phase, transmitter position, orientation and clock. We further demonstrate the near-optimal detection capability of the proposed detector compared with generic coherent detectors and validate the effectiveness of phase information exploitation via numerical simulations. [ABSTRACT FROM AUTHOR]

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional- $N$ mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional- $N$ mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from −250.1 to −251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than −70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5–7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm2. [ABSTRACT FROM AUTHOR]

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (< 0.2 dB) and a negligible area penalty. A full-range phase detector with improved detection resolution is proposed, enabling an amplitude-insensitive phase detection. Fabricated in a 22 nm FD-SOI process, the sensor prototype occupies a silicon area of 0.024 mm2 and consumes 13.2 mW power. The sensor demonstrates a wide detection range with $\vert \Gamma \vert $ up to 0.7 (VSWR 5.67) in a load-pull test at 28 GHz. From $\Gamma $ circle of 0.2 up to 0.7, the maximum detection errors in the magnitude and phase of the $\Gamma $ are 0.14° and 40°, respectively. [ABSTRACT FROM AUTHOR]

Most conventional vital-sign radars cannot easily detect human vital sign signals under nonperiodic body movement. This article presents a novel frequency-locked loop (FLL) radar that can track the phase changes that are caused by nonperiodic body movement. A gain/phase detector and a cross correlation function (CCF) in the FLL radar greatly reduce the second harmonic, the intermodulation terms between vital sign signals and nonperiodic body movement noise, enhancing both the signal-to-noise ratio and the accuracy of detection of the vital signs. Measurements indicated that the implemented 2.4-GHz FLL radar with a gain/phase detector and CCF can effectively detect the human respiration rate (RR) and heart rate (HR) under nonperiodic body movement. Using a chest belt as the measurement reference, the standard deviation (SD) of RR and HR measurements were 1.27 and 5.69 beats/min, respectively, when the seated subject under test (SUT) swung nonperiodically his upper body. When the SUT walked away from the radar naturally at 2.6 km/h, the implemented FLL radar measured RR and HR with SDs of 2.67 and 8.28 beats/min, respectively. [ABSTRACT FROM AUTHOR]

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated. [ABSTRACT FROM AUTHOR]

Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed. [ABSTRACT FROM AUTHOR]

This article presents an amplitude and 360° phase shift array measurement system. The basic cell of the measurement system uses a novel amplitude and phase detector based on switched dual multipliers. The phase shift measurement is characterized using an analog phase detector (mixer), detecting a maximum range of ±90°, and a double multiplication of the input signals, in phase and phase shifted. This method broadens the frequency and amplitude range beyond other solutions that require fulfilling the quadrature condition. This method broadens the frequency and amplitude beyond other solutions requiring fulfilling the quadrature condition or phase and amplitude balance. Thus, it enables to compensate significant phase imbalance in the 90° hybrid or use amplitudes out of the range that ensures the switching operation of mixer diodes. The circuit calibration that allows compensation for errors (amplitude, phase shift, mismatching, etc.) is detailed, and its relation to the required measurement accuracy is discussed. The design can be easily extrapolated to other frequency ranges because it uses commercial RF devices available in a wide frequency range and avoids the need of crossing lines or complex 90° hybrid. A prototype with $3 \times 3$ cells has been built to evaluate various test conditions on $1 \times 3$ cell configurations that show the advantages of the procedure. It should be highlighted that the cell prototype uses devices that will be operating outside the frequency and amplitude ranges recommended by their manufacturers. A calibration from 2.6 to 6 GHz and −15 to −3 dBm was performed to evaluate the measurement errors. An analysis of the isolation between cells and different calibration configurations is performed to analyze the measurement errors. Measurements show compensation of +30°/−25° phase imbalance and 13-dB power lower than mixer manufacturer recommendation. [ABSTRACT FROM AUTHOR]

This article presents a circuit for the precise vertical landing of drones based on a three phase-shifts detection of a single frequency transmitted from the landing point. The circuit can be considered as a new navigation sensor that assists in guidance corrections for landing at a specific point. The circuit has three inputs to which the signal transmitted from an oscillator located at the landing point arrives with different delays. The input signals are combined in pairs in each of the three analog phase detectors, after having passed through 3 dB at 90° hybrid couplers that guarantee a theoretical nonambiguous phase shift range of ±90°. Each output has a voltage that is proportional to the phase shift between each of the input signals, which in turn depends on the position relative to the landing point. A simple landing algorithm based on phase shift values is proposed, which could be integrated into the same flight control platform, thus avoiding the need to add additional processing components. To demonstrate the feasibility of the proposed design, a triangular phase shift detector prototype has been implemented using commercial devices. Calibration and measurements at 2.46 GHz show a dynamic range of 30 dB and a nonambiguous detection range of ±80° in the worst cases. Those specs let us track the drone during the landing maneuver in an inverted cone formed by a surface with a ±4.19 m radius at 10 m high and the landing point. [ABSTRACT FROM AUTHOR]

An accurate and cost-effective islanding detection is in a great need for distributed generation (DG) integration. An onsite contactless islanding detection scheme is proposed in this article, based on a small number of tiny and portable electric field (EF) sensors. In contrast to the existing mainstream detection techniques, which are heavily depended on the instrument transformer measurement in substations, the proposed contactless scheme is able to be deployed on the ground below the overhead feeders, enabled by a compact EF sensor and the associated accurate frequency measurement algorithm. The effectiveness, robustness, efficiency, and security advantages of the proposed method are investigated and verified by the simulations using various feeder configurations. It is further supported by the laboratory experiments based on a scale-down overhead feeder testbed. [ABSTRACT FROM AUTHOR]

Purpose: To evaluate vessel assessment in virtual monoenergetic images (VMI40keV) and virtual-non-contrast images (VNC) derived from venous phase spectral detector computed tomography (SDCT) acquisitions in comparison to arterial phase and true non-contrast (TNC) images. Methods: Triphasic abdominal SDCT was performed in 25 patients including TNC, arterial and venous phase. VMI40keV and VNC were reconstructed from the venous phase and compared to conventional arterial-phase images (CIart), TNC and conventional venous-phase images (CIven). Vessel contrast and virtual contrast removal were analyzed with region-of-interest-based measurements and in a qualitative assessment. Results: Quantitative analysis revealed no significant attenuation differences between TNC and VNC in arterial vessels (p-range 0.07–0.47) except for the renal artery (p = 0.011). For venous vessels, significant differences between TNC and VNC were found for all veins (p < 0.001) except the inferior vena cava (p = 0.26), yet these differences remained within a 10 HU range in most patients. No significant attenuation differences were found between CIart/VMI40keV in arterial vessels (p-range 0.06–0.86). Contrast-to-noise ratio provided by VMI40keV and CIart was equivalent for all arterial vessels assessed (p-range 0.14–0.91). Qualitatively, VMI40keV showed similar enhancement of abdominal and pelvic arteries as CIart and VNC were rated comparable to TNC. Conclusion: Our study suggests that VNC and VMI40keV derived from single venous-phase SDCT offer comparable assessment of major abdominal vessels as provided by routine triphasic examinations, if no dynamic contrast information is required. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process–voltage–temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 × 64 pixels over an area of 2.4 × 2.4 cm2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution. [ABSTRACT FROM AUTHOR]

This article presents a fractional- ${N}$ frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops. A digital frequency-error recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional- ${N}$ operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm2. It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 $\mu \text{s}$. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional- ${N}$ and integer- ${N}$ modes, respectively. The worst-case in-band fractional spur is at −61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of −250.6 dB for the fractional- ${N}$ channels. [ABSTRACT FROM AUTHOR]

Baikal-GVD is a deep-underwater neutrino detector of cubic-kilometer scale. It is designed to detect astrophysical neutrinos up to multi-PeV energies and beyond. The deployment of this facility began in spring 2015. Since April 2020, the detector includes seven clusters, each consisting of eight strings carrying in total 288 optical modules located at depths of 750 to 1275 m. By the end of the first phase of construction of the detector in 2024, it is planned to deploy 15 clusters, whereby an effective volume of 0.75 km for detecting high-energy cascades would be reached. The design and status of the Baikal-GVD detector are described in the present article along with selected results of data analysis. [ABSTRACT FROM AUTHOR]

This article proposes a novel multibeam dual-frequency sensor system to assess the quality of thick rind fruits based on phase difference between lower- and higher-frequency reflection coefficients ($\Phi _{12}$). The proposed sensor system consists of five dual-band antennas and a customized circuit that approximates lower- and higher-frequency phase difference. The main components of the customized circuit are down-conversion mixers and a phase detector module. For comparison, simulations were initially carried out using single- (1 GHz) and dual-frequency (1 GHz/2.3 GHz) sensor systems, and results indicated lower accuracy in classification of thick rind fruits of the single-frequency scheme. As a result, a dual-frequency sensor prototype was fabricated and experimented with normal and granulated plastic pomelo models and real pomelo fruits. The experimental results revealed that the average $\Phi _{12}$ of the normal and granulated pomelos are almost identical, while the standard deviation (SD) of $\Phi _{12}$ of the granulated pomelo is significantly larger than the normal pomelo. SD is thus used as the determinant of pomelo quality. The multibeam 1-GHz/2.3-GHz dual-frequency sensor system efficiently differentiates between normal and granulated pomelo fruits. As such, the proposed sensor system is operationally appropriate for quality control of thick rind fruits. [ABSTRACT FROM AUTHOR]

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs. [ABSTRACT FROM AUTHOR]

This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm2, implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit. [ABSTRACT FROM AUTHOR]

This article presents a simple, cost-effective system for complex measurements of the field radiated by an antenna. In particular, the proposed architecture is based on an array of antenna probes connected to a set of phase difference detectors and a power detector. Phase difference measurements are processed to recover the phase of the antenna under test. The main novelty of the proposed system is that it does not require regular sampling, making it suitable for in situ antenna measurements. The influence of parameters, such as the number of antennas composing the array (and hence the number of phase difference detectors) and the positioning errors, is analyzed. The proposed architecture, implemented with off-the-shelf hardware, has been assessed for antenna measurement and diagnostics. A discussion of the issues related to the implementation of the system has been included, as well as the proposed solutions to improve its accuracy. Finally, diagnostics and radiation pattern measurement results are compared with those calculated with other phaseless techniques. [ABSTRACT FROM AUTHOR]

In this article, a phase-locked loop (PLL) rotor position and speed observer, including an integrated decoupled stator current observer, is proposed for wide-speed-range sensorless control of permanent magnet synchronous motor (PMSM) drives. This new PLL scheme consists of two interconnected observers: 1) a second-order PLL position observer using the direct current error as correction term and 2) a third-order extended Luenberger speed observer, based on the mechanical model of the drive, using the quadrature current error as the correction term. The estimated speed is just an unrefined reference for the position integrator, and it is further corrected by the PLL. The current observer is a subsystem integrated as a PLL phase detector. Key relations between the current errors and the position and speed errors are proven, and a practical two-step observer design method is presented. A method for real-time identification of the stator resistance at low speeds and of the permanent magnet flux at high speeds is proposed, using the current errors in the current reference frame. Experimental results for a 0.5-kW surface-mounted PMSM drive confirm the effectiveness, excellent dynamic performance, and robustness of the new PLL observer. Stable motor and generator operation at 15 r/min (0.01 p.u.) with ramp and step speed reversals, high-speed operation, and stator resistance adaptation is shown. [ABSTRACT FROM AUTHOR]

Small displacement detection capability becomes an important key for developing non-contact sensor for human respiration based on radar system. Frequency modulated continuous wave (FMCW) radar has been widely studied and applied for many applications. With respect to the conventional perspective, large bandwidth is needed for detecting the small displacement related to the human respiration. Meanwhile, extracting the respiration pattern from Doppler response has a drawback in identifying the small displacement location. In this paper, the modification on FMCW system was proposed for obtaining the capability in detecting the human respiration and its distance from the radar. Detecting the phase value of the low pass filter (LPF), output from conventional FMCW was investigated and applied as a modification concept. The pattern, rate and amplitude of respiration are extracted from phase detector output. Beat frequency detection is still elaborated for synthesising the reference signal for phase detection. The result shows that the modified FMCW system proposed the capability of detecting the rate and amplitude respiration and location of the target. [ABSTRACT FROM AUTHOR]

This brief presents a new frequency acquisition method using a semirotational frequency detection (SRFD) algorithm for referenceless clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the bang–bang phase detector (BBPD) outputs to estimate the current phase state and detects the frequency mismatch between the input data and the sampling clock. The voltage-controlled oscillator (VCO)-track path in a digital loop filter (DLF) enables online calibration of a drifted frequency of the VCO caused by temperature or voltage variation after a frequency acquisition. The proposed algorithm can be implemented as a digitally synthesized circuit, lowering design efforts for referenceless CDRs. A 10-Gb/s transceiver IC with the proposed algorithm, fabricated in a 65-nm CMOS process, demonstrates successful recovery of the input phase without any reference clock. [ABSTRACT FROM AUTHOR]

A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronization and 1-to-8 deserialization for converting high-speed scalable low-voltage signals into low-speed low-voltage complementary metal-oxide semiconductor signals. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise owing to the use of the multiple bits supplied from the deserializer as a result of the phase detector for the skew calibration. It is performed via a four-step sequential process to use the minimum time delay. The proposed receiver bridge chip is implemented using a 0.11 $\mu \text{m}$ CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the signal recovered using the proposed receiver is 50 ps at a data rate of 5.0 Gbps/lane on a printed circuit board FR-4 10 inch channel. The proposed skew calibration reduces the time skew among the four data lanes and one clock lane to less than 10 ps. [ABSTRACT FROM AUTHOR]

The GERmanium Detector Array (Gerda) is a low background experiment located at the Laboratori Nazionali del Gran Sasso in Italy, which searches for neutrinoless double-beta decay of 76 Ge into 76 Se+2e - . Gerda has been conceived in two phases. Phase II, which started in December 2015, features several novelties including 30 new 76Ge enriched detectors. These were manufactured according to the Broad Energy Germanium (BEGe) detector design that has a better background discrimination capability and energy resolution compared to formerly widely-used types. Prior to their installation, the new BEGe detectors were mounted in vacuum cryostats and characterized in detail in the Hades underground laboratory in Belgium. This paper describes the properties and the overall performance of these detectors during operation in vacuum. The characterization campaign provided not only direct input for Gerda Phase II data collection and analyses, but also allowed to study detector phenomena, detector correlations as well as to test the accuracy of pulse shape simulation codes. [ABSTRACT FROM AUTHOR]

A full-rate clock and data recovery loop employs a three-stage ring voltage-controlled oscillator, a master–slave passive sampler as both a phase detector and a filter, and a new flip-flop to achieve a loop bandwidth of 170 MHz. Implemented in 45-nm CMOS technology, the circuit occupies an area of 14 $\mu \text{m}\,\,\times $ 26 $\mu \text{m}$ and exhibits a jitter tolerance of 2 UI at 5 MHz and a recovered clock jitter of 459 fs with 231 – 1 pseudorandom bit sequence. [ABSTRACT FROM AUTHOR]

This article presents a simple, cost-effective system for complex measurements of the field radiated by an antenna. In particular, the proposed architecture is based on an array of antenna probes connected to a set of phase difference detectors and a power detector. Phase difference measurements are processed to recover the phase of the antenna under test. The main novelty of the proposed system is that it does not require regular sampling, making it suitable for in situ antenna measurements. The influence of parameters, such as the number of antennas composing the array (and hence the number of phase difference detectors) and the positioning errors, is analyzed. The proposed architecture, implemented with off-the-shelf hardware, has been assessed for antenna measurement and diagnostics. A discussion of the issues related to the implementation of the system has been included, as well as the proposed solutions to improve its accuracy. Finally, diagnostics and radiation pattern measurement results are compared with those calculated with other phaseless techniques. [ABSTRACT FROM AUTHOR]

Halved phase-only multiple input multiple output (HPO-MIMO) completes wireless transmission based on $\pi$ -periodic phase measurements, which are directly acquired by phase detectors at the base station. However, existing synchronization algorithms for MIMO can no longer be applied into HPO-MIMO, because they work under complete measurements with both magnitude and phase information but HPO-MIMO loses magnitude information completely. This correspondence paper proposes a joint time and frequency synchronization algorithm for HPO-MIMO, which exploits the repeatability of a pilot preamble. Starting-time and carrier frequency offset (CFO) are jointly estimated under a grid-searching manner. At first, continuous starting-time and CFO estimation are uniformly sampled from their potential value ranges. On all potential starting-time points, the received phase measurements are uniformly sliced according to the repetition structure of the preamble, and then the phase rotations due to CFO are removed based on each potential CFO value. The shifted phase measurements would show strong similarities if CFO is successfully compensated. The similarities among these sliced phase sequences are characterized by a metric named phase sequence distance (PSD). They are summed up as a final PSD, whose minimum value corresponds to the estimated starting time and CFO. Simulation results validate the effectiveness of the synchronization algorithm under different signal-to-noise ratios and lengths of preamble. HPO-MIMO with our synchronization algorithm can even perform similarly as its perfect-synchronized correspondence. [ABSTRACT FROM AUTHOR]

This paper proposes a method to improve the accuracy of an absolute magnetic encoder by using harmonic rejection (HR) and a dual-phase-locked loop (DPLL). The encoder consists of two permanent magnets: an edge-located multipolar magnet (MPM) and a center-located bipolar magnet, in which the signal-processing accuracy of the MPM is crucial for achieving high accuracy of the entire encoder. However, the MPM signals are disturbed by nonidealities such as dc offsets, amplitude mismatch, low- and high-order harmonics, and random noises. In this paper, the HR approach investigates the characteristics of nonidealities of the phase detector and rejects them by using gradient descent. In addition, the DPLL remains robust by maintaining a zero steady-state error during a phase jump, a constant frequency, and a ramp frequency. The proposed method is simulated with MATLAB software and implemented in ARM STM32F407ZG. The obtained results demonstrate efficient performance. This method can be applied to any use of quadrature sinusoidal signals, such as in power grids and in permanent-magnet synchronous motor phase detection. [ABSTRACT FROM AUTHOR]

An in-line type X-band phase detector is presented in this letter. It is constructed by a power combiner and a capacitive power sensor with clamped-clamped beam to obtain large dynamic range with respect to RF power. The fabrication process is based on MEMS technology. The experiments show that the return loss is smaller than −12.3 dB over X-band, the isolation is better than −9.1 dB and the insertion loss is around −3.5 dB. The conversion between phase, power, and capacitance is accomplished inside the detector for phase detection from 0 to 180°. The varying capacitance of the beam can sustain a dynamic range of 0.25 ~ 2 W with satisfactory detection sensitivity, 163.8aF/deg. at 2W. Third-order intermodulation distortion (IM3) of the detector is rather small and the IIP3 is about 37.4 dBm for 10-kHz frequency interval. [ABSTRACT FROM AUTHOR]

A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm2. The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz. [ABSTRACT FROM AUTHOR]

A referenceless single-loop clock and data recovery (CDR) circuit with a half-rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle-slip in the half-rate linear PD and its relationship with the frequency acquisition are described in detail. The single-loop CDR consists of a conventional phase-tracking loop and a frequency-tracking unit, referred to as the cycle-slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak-to-peak jitter of the recovered clock are 2.40 psrms and 21.4 pspp, respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3 UIpp. The CDR occupies 0.105mm2 and consumes 26mW at 8 Gb/s from a 1.0 V supply. [ABSTRACT FROM AUTHOR]

An analysis of a frequency detection capability of the Alexander phase detector is described. Based on the analysis, a simple modified implementation achieving unilateral frequency acquisition is proposed. The probability of the output occurrence and the frequency detection gain are calculated and verified by simulation. The gain curves show that the proposed phase-frequency detector (PFD) has a unilateral frequency detection capability without a range limitation. The capability is demonstrated through transient simulation of a PLL-based clock and data recovery (CDR) utilising the proposed PFD. The CDR achieves both phase and frequency acquisitions when the initial clock frequency is lower than the data rate. Moreover, the seamless transition from frequency locking to phase locking is obtained. [ABSTRACT FROM AUTHOR]