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Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points. [ABSTRACT FROM AUTHOR]

This article presents a commutated-inductor–capacitor (commutated- $LC$) or switched- $LC$ circuit that acts as a radio frequency (RF) delay line. Thanks to its linear-periodically time-varying (LPTV) operation and fully passive implementation, it concurrently achieves long maximum delays, fine delay tuning steps, and wide instantaneous bandwidths while being low loss and highly linear. Unlike existing LPTV switched-capacitor broadband delays, the introduction of inductors in the proposed commutated- $LC$ delay circuit provides a new degree of freedom, allowing it to operate at a much higher RF with a wider instantaneous bandwidth. A proof-of-concept prototype in a 65-nm CMOS process demonstrates a measured 1.3-GHz 3-dB bandwidth around a 4.3-GHz RF, i.e., a 30% fractional bandwidth, when clocked at 250 MHz. The measured maximum delay is 1.4 ns with a 23-dB loss and noise figure; this loss or noise is orders of magnitude lower compared with fully passive linear-time-invariant RF delay lines operating at a similar frequency with the same delay. The measured IIP3 is +16 dBm. [ABSTRACT FROM AUTHOR]

In this work, we theoretically investigate the superluminal and subluminal reflected group delay in an air-Weyl semimetal film-Weyl semimetal substrate layered structure by using the $4\times $ 4 transfer matrix method. We show a tunable transition between positive and negative group delays of reflection pulse in this layered structure by controlling the properties of the Weyl Semimetal layer, and we also reveal its mechanism to modify the propagation properties of the light pulse reflected from this structure. It is demonstrated that the reflected group delays are tunable from positive to negative values and vice versa, which are adjusted by tuning the incident angle, thickness of Weyl semimetal film, tilt parameter, and Fermi energy. The control of the magnitude and the sign of the reflected group delay of light propagation represent a key point in slow and fast light technologies. Our results are helpful in controlling pulse propagations and are useful for the design of Weyl semimetal-based delay devices. [ABSTRACT FROM AUTHOR]

The serpentine delay line (SDL) is commonly used as one kind of typical true time delay lines (TDLs) with periodic strong reflection points (SRPs). However, the Hilbert fractal curve delay lines (HFCDLs), with the same circuit area and the same spacing between the adjacent segment lines, are proven to have quite different SRPs with improved performance. An analytic analysis model is used to investigate the SRPs of the two-order and three-order HFCDLs, respectively, in which the structure symmetry is fully considered to make the relevant adjacent structure equivalent to a pair of parallel dual lines. Thus, the accumulated far-end crosstalk (FEXT) is derived in the HFCDLs, and the implicit periodic SRPs are revealed. Furthermore, the iterated two-order and three-order HFCDLs are investigated to validate the analysis model. Subsequently, the periodically loaded transmission line (PLTL) with and without strategic discontinuous structured guard lines (DSGLs) is, respectively, utilized in the three-order and two-order HFCDLs, and thus, the proposed structures possess better wideband cancelation of the FEXT accordingly. In the ultrawideband (UWB) range of dc–51 GHz, the typical return loss (RL) is less than 20 dB for the proposed two-order HFCDL and less than 15 dB for the proposed three-order HFCDL. Meanwhile, the fluctuations are eliminated in the group delay (GD) for the proposed two-order HFCDL. For the proposed three-order HFCDL, the delay fluctuations are observed at the high end of the UWB due to the enhanced near-end crosstalk (NEXT), while the delay fluctuations less than 72.2 ps are still obtained in the range of dc–35 GHz. [ABSTRACT FROM AUTHOR]

We propose a novel continuously tunable delay line in X-cut lithium niobate thin film driven by graphene electrodes, featuring low power consumption and low half-wave voltage-length product. The use of the graphene electrodes combined with the air slots makes the device quite low power consumption. Our designed device, which has a footprint of 8.9 mm × 1.9 mm, is capable of providing a continuously tunable delay range from 0 to 100 ps with minimum 3 dB bandwidth of >20 GHz. By optimizing the width of the waveguide core and the distance between the graphene and the waveguide core, we can obtain the low power consumption and low voltage - length product VπL = 1.12 V·cm at 1550 nm when w = 2 μm and d = 0.3 μm. In addition, the graphene electrode has negligible light absorption with w = 2 μm and d = 0.3 μm, the switching power is 151 mW without air slots, and the switching power is 95.36 mW with air slots etching depth of 5.3 μm formed on both sides of the waveguides. And further, the air slots formed on both sides and at the bottom of the waveguides make a low switching power of 2.85 mW. [ABSTRACT FROM AUTHOR]

In this research study, a novel hybrid approach to beam steering based on the combination of true time delay and phase shift to enable continuous beam steering with minimal beam squint in wideband mm-wave transceivers is investigated. With modern high-speed communication links in the mm-wave spectrum requiring ever higher bandwidths, and losses increasing with frequency, there is a need for steerable arrays in mobile applications. This steering capability is commonly realized by phase shifters, which enable continuous beam direction control, but produce significant beam squint at large bandwidths or steering directions. An alternative is to use a time-delayed control, which resolves the squint issue but covers only a limited number of beam directions, producing considerable loss and being large in size. This research work presents the first 2-bit time delay stage operating above 200 GHz. In addition, a novel approach is described to enable broadband continuous beam control with minimal beam squint; this is achieved by combining the time delay circuit with a 90° vector-sum phase shifter. To prove the concept, the circuit is realized in a 130-nm SiGe Bipolar Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) technology. At 4.33 mW of dc power consumption, the small-signal gain is −8.6 dB at a 3-dB band of 220–250 GHz, resulting in 12.8% of relative bandwidth. The time delay stage provides coarse beam direction control with a maximum steering angle of 43.9° resulting from a maximum delay of 1.47 ps with a resolution of 0.39 ps. Across all tuning states, the root-mean-square delay error is less than 23.7 fs. The following phase shifter enables fine direction control while also compensating ±1.5 dB of gain variation resulting from the time delay. This is achieved while reducing the area consumption to half of what is required for comparable true time delay circuits. In a minimal $2\times 1$ antenna array, this enables continuous beam direction control between ±54.6° while limiting the beam squint to less than 2.5°, equating to a more than 75% reduction in comparison to the common phase shift approach. [ABSTRACT FROM AUTHOR]

A CMOS distributed power amplifier (DPA) for quantum key distribution (QKD) system to drive an electro-optical phase modulator is developed. Due to the requirement of amplifying high-speed non-return-to-zero (NRZ) signal, our design is supposed to provide enough bandwidth, including dc. To achieve sharp roll-off performance, the m-derived filter section is applied to realize the artificial transmission line rather than the constant-k section. Combining the theory analysis and simulation, the bridges between gain ripple, group delay fluctuation, or maximum linear output power and the parameters of time domain waveform are established. Furthermore, through analyzing the attenuation and delay of the transmission line, approaches to improving the frequency performance, such as gain variation and group delay fluctuation, are provided. The DPA is implemented in the 0.25- $\mu \text{m}$ CMOS process and achieves a bandwidth of dc-12 GHz, a gain of 11.54 dB with variation of ±1.34 dB, a group delay of 400 ps with fluctuation of about 100 ps, and a maximum output 1-dB compression point of 20.6 dBm. When a 1-Gb/s NRZ signal is applied to the DPA, the rise and fall times are both about 90 ps. The amplifier occupies an area of 2.8 mm $\times0.94$ mm including pads and adopts the flip-chip package with low-temperature co-fired ceramic (LTCC) substrate. [ABSTRACT FROM AUTHOR]

We present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.0625MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0 GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607ps $_{rms}$ across 156.25-312.5MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9ps $_{rms}$ across 2.5-5.0 GHz output frequency with 0.98-1.06mW/GHz power dissipation. [ABSTRACT FROM AUTHOR]

To reduce the area occupied by delay lines for the 5G sub-6-GHz frequency band, a 3-D rolled-up structure is presented in this letter. According to the rules proposed in this letter, a conventional planar interdigital delay line is rolled up, transforming the initially planar device into a 3-D spiral geometry. When rolling the device into 1 turn, the area occupied by the rolled-up interdigital delay line is reduced by over 65% while maintaining similar performance to the unrolled device. From 1 to 6 GHz, the return loss of the input and outputs port is greater than 13.1 dB, and the insertion loss is less than 3 dB. The group delay is 1.8 ns±5% over the operating band. [ABSTRACT FROM AUTHOR]

In classical synchronous designs, supply voltage droops can be handled by accounting for them in clock margins. However, this results in a significant performance hit even if droops are rare. In contrast, adaptive strategies detect such potentially hazardous events and either initiate a rollback to a previous state or proactively reduce clock speed in order to prevent timing violations. The performance of such solutions critically depends on a very fast response to droops. State-of-the-art solutions incur synchronization delays in the order of several clock cycles to avoid, with sufficient probability, that the clock signal is affected by metastability. We present an all-digital circuit that can respond to droops within a fraction of a clock cycle. This is achieved by using potentially metastable measurement values to delay clock signals while they undergo synchronization, instead of after they are synchronized. The challenge is to ensure that this strategy does not lead to harmful glitches or metastable upsets within the circuit. To this end, we verify our solution by formally proving correctness. We complement our findings by simulations of a 65-nm ASIC design confirming the results of our analysis. [ABSTRACT FROM AUTHOR]

Photoacoustic tomography (PAT) is an emerging technology for biomedical imaging that combines the superiorities of high optical contrast and acoustic penetration. In the PAT system, more PA signals are preferred to be detected from full field of view to reconstruct the PA images with higher fidelity. However, the requirement for more PA signals’ detection leads to more time consumption for single-channel scanning-based PAT system or higher cost of data acquisition (DAQ) module for an array-based PAT system. To address this issue, we proposed a programmable acoustic delay-line (PADL) module to reduce DAQ cost and accelerate imaging speed for PAT system. The module is based on bidirectional conversion between acoustic signals and electrical signals, including ultrasound transmission in between to provide sufficient time delay. The acoustic delay-line module achieves tens or hundreds of microseconds’ delay for each channel and is controlled by a programmable control unit. In this work, it achieves to merge four inputs of PA signals into one output signal, which can be recovered into original four PA signals in the digital domain after DAQ. The imaging experiments of pencil leads embedded in agar phantom are conducted by the PAT system equipped with the proposed PADL module, which demonstrated its feasibility to reduce the cost of the PAT system. An in vivo study of human finger PAT imaging with delay-line module verified its feasibility for biomedical imaging applications. [ABSTRACT FROM AUTHOR]

In this article, a compact distributed septuple-band negative group delay circuit (NGDC) is proposed and analyzed. It is mainly composed of a high–low–high step-impedance microstrip line with an E-shaped groove and two T-shaped open stubs. This NGDC was first simulated and then fabricated by using a conventional printed circuit board (PCB) process with the substrate of RO4350. To investigate the operational mechanism of the NGDC, an equivalent circuit, consisting of nine transmission lines, four series–parallel LC resonant circuits, and two T-type series LC resonant circuits, has been developed and analyzed. It is found that the theoretical group delay characteristic calculated from the equivalent circuit agrees well both with the simulated data by using ADS as well as HFSS and with the experimental results. The measured seven NGD resonant frequencies occur at 2.03, 2.84, 8.14, 8.74, 13.0, 16.02, and 18.46 GHz, and the corresponding NGD values read −3.65, −3.04, −1.73, −3.23, −1.16, −1.20, and −1.47 ns. The dimensions of the presented passive NGDC are only 25 mm $\times22$ mm without using any lumped components. [ABSTRACT FROM AUTHOR]

$N$ -path true time delay (TTD) circuits are highly attractive due to their high delay-bandwidth product, wideband response, scalability, and small size. However, in its standalone form, it cannot provide wideband input and output matching. To overcome these issues, we present a modified circuit of the $N$ -path TTD that includes an input low-noise amplifier (LNA) and an output buffer. The $N$ -path TTD response and its nonideal properties are analyzed further. A design guide is suggested, and an alternative isolated sampling switch is proposed. We present a 65-nm CMOS dedicated implementation, where the fine-tuning of the TTD is achieved by introducing two synchronized external local oscillator (LO) signals, with a relative shift between them. The core chip size is $0.32 \,\times \,0.575$ mm2, and its power consumption is 30 mW for all delay states. In our implementation, we achieve a delay range of 1 ns for bandwidth (BW) of 0.2–3 GHz with a gain standard deviation (STD) of less than 0.14 dB between delay states and a relative delay STD of less than 10 ps (1%) over frequency. [ABSTRACT FROM AUTHOR]

A single-layer prephased 1-bit reflective metasurface is proposed to achieve single-beam radiation patterns under normally incident plane waves. By integrating the true-time delay lines with the prephase technique, the proposed design resolves the inherent symmetric beam issue of the conventional 1-bit reflective metasurface design in a single-layer design. To verify the proposed design, three 1-bit reflective metasurfaces comprising 20 × 20 unit cells with single beams pointing separately at $-15^{\circ }$ , $15^{\circ }$ , and $30^{\circ }$ are designed and measured over frequencies of 35.0–43.0 GHz. Simulated and measured results show that the proposed prephased 1-bit reflective metasurface can achieve single-beam patterns under normally incident plane waves using only one layer. [ABSTRACT FROM AUTHOR]

We present a low-power and low jitter two-stage 2.46–4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an $8\times $ clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a $64\times $ – $128\times $ clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fsrms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving −53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fsrms at 4.92 GHz, −28.2-dBc reference spur, and 3-mW power consumption. [ABSTRACT FROM AUTHOR]

A TDC-based temperature sensor is implemented using 0.18- $\mu {\mathrm{ m}}$ CMOS technology for thermotherapy. The temperature sensor is composed of a temperature-to-pulse generator (TPG) and a time-to-digital converter (TDC). The TPG consists of two delay lines with different temperature coefficients, where one of the delay lines is realized by using the temperature compensation, so it is almost temperature independent. The TDC is based on a pulse shrinking architecture, where the number of the shrinking element and unit delay determine how the pulse is reduced in each cycle. The design flow is first proposed to facilitate the design process. Moreover, the impact of process variation is considered for the shrinking element. The resolution of 0.054°C is achieved by the temperature sensor. After the two-point calibration, the inaccuracy is ± 0.2°C for the temperature range from 25°C to 45°C. The temperature sensor consumes 0.65 uJ for each sample while achieving the conversion time of 100 ms. The chip size is 0.47 mm2. [ABSTRACT FROM AUTHOR]

We presented a novel integrated dielectric chip sensor based on time-domain sensing technique. The sensor is based on a dielectric constant-dependent delay line with a load capacitor realized by an interdigitated capacitor (IDC). The IDC exposed to the material under test (MUT) is used to sense the change of MUT’s dielectric constant. The delay line is utilized to generate a delay proportional to the measured dielectric constant. To improve the sensitivity with a smaller area, a time-amplifier (TA) is employed to amplify the delay change. As a proof of concept, the sensor has been calibrated with Ethyl-acetate, Butyraldehyde, Isopropanol and Ethanol. Ethanol and Ethyl-acetate mixture solutions, in steps of 20% of concentration change, have been used to demonstrate the performance of the sensor. The chip is fabricated in a 55 nm CMOS technology with a core area of 0.105 mm $\times $ mm. It only consumes 0.13 mA from a single 1.2 V. Compared with other methods, this method has more advantages in sensor array applications. [ABSTRACT FROM AUTHOR]

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction. [ABSTRACT FROM AUTHOR]

In the Internet of Vehicles (IoV) scenarios, vehicles are equipped with computing resources to support vehicle-oriented IoV applications. Meanwhile, these computing resources can be also leveraged to enhance the task processing performance for the devices in Multi-access Edge Computing (MEC) scenarios, and alleviate the load of edge servers. Existing research works rarely consider the resource utilization of moving vehicles, which can be an important complement to the MEC schemes with the assistance of parked vehicles. In this paper, a joint task offloading and resource allocation scheme is proposed for a parked-and-moving-vehicles-assisted MEC scenario consisting of multiple devices, parked vehicles, and moving vehicles covered by a Base Station (BS) equipped with an edge server. The tasks of the devices can be either offloaded to the BS or further offloaded from the BS to the vehicles. The service time that a moving vehicle can provide its task offloading service before it moves out of the coverage of the BS, are taken into account of our system model. The aim of our scheme it to minimize the total priority-weighted task processing delay for all the devices through offloading the tasks to the edge server or to the vehicles, allocating the wireless channels of the BS, and allocating the computing resource of the edge server and the vehicles. A generalized benders decomposition and reformulation linearization-based iterative algorithm is designed to obtain the optimal solution to the optimization problem, and a two-stage heuristic algorithm is also given to provide near-optimal solutions with low computational complexity. The simulation results demonstrate the superiority of our scheme in seven different scenarios by comparing it with three other schemes. [ABSTRACT FROM AUTHOR]

Multi-access edge computing (MEC) has been one promising solution to reduce the computation delay of wireless devices. Due to the high spectrum efficiency of non-orthogonal multiple access (NOMA), this paper studies the single-user multi-edge-server MEC system based on downlink NOMA, aiming to minimize task computation delay by jointly optimizing the NOMA-based transmission duration (TD) and workload offloading allocation (WOA) among edge computing servers. This task computation delay minimization (CDM) problem is formulated as a nonconvex optimization problem. To solve the CDM problem efficiently, we decompose it into the sub-problem of determining the optimal WOA with a given TD and the top-problem of optimizing the TD. For the sub-problem, we first derive its some important properties and then design an efficient channel quality ranking based algorithm to obtain the optimal WOA. We solve the top-problem for the static-channel and dynamic-channel scenarios, respectively. For the static-channel scenario, we design an optimal algorithm which only apply once the golden section search method to obtain the optimal TD of first task and directly obtain the optimal offloading solution for any consequently arrived task with different workloads. For the dynamic-channel scenario where the channel qualities from the wireless device to the edge-computing servers are varying, it is critical to quickly determine the current task’s offloading solution under the current channel state and task workload, which is very challenging for the traditional optimization methods. In order to conquer this challenge, we propose the deep reinforcement learning (DRL) based algorithm, which can obtain the near-optimal offloading solution instantly after enough learning. Finally, we validate through simulations the advantages of NOMA over frequency division multiple access (FDMA). [ABSTRACT FROM AUTHOR]

In this paper, an iterative algorithm is developed to combine time shifted traces in pulsed terahertz time domain spectroscopy (THz-TDS). This method intends to correct errors due to mechanical sampling in the trailing ends of the traces in systems that utilize a combination of a fast voice coil optical delay line and a slow long delay range one. The algorithm works by iteratively combining three basic modifications on the trace shape to match the overlapping areas of consecutive time windows. In order to validate the method, both simulated and experimental traces affected by ODL distortions are stitched. Proper stitching is shown to mitigate the increase of noise floor and the frequency shift of spectral resonances that arises with direct stitching, i.e. just compensating for the offset between traces. An enhancement in acquisition speed by a factor 7 in comparison to conventional lock-in detection based on a long range optical delay line is shown in tests with the experimental setup available. [ABSTRACT FROM AUTHOR]

Energy-efficient communication technologies are a key enabler for many IoT applications. Many existing communication protocols are based on duty-cycling techniques, that have an inherent tradeoff between delay and energy consumption. In the field of sensor networks, wake-up receivers have been investigated to overcome these problems and to further reduce energy consumption. We now go one step further and investigate the use of wake-up receivers in combination with IEEE 802.11 WLAN. We extend the protocol used to communicate between the access point and the client to introduce a wake-up signal. This can be implemented in a way that is fully compatible with existing wireless LAN (WLAN) standards, thus, it can be deployed gradually with little effort and no need to change existing systems. As a proof of concept and to perform first lab experiments, we developed a hardware prototype using a selective wake-up receiver and off-the-shelf USB-WLAN dongles. All experimental results are verified using an analytical model and a detailed simulation study. We show that our wake-up WLAN can provide connectivity for low-power devices with low delays and low energy consumption at the same time. [ABSTRACT FROM AUTHOR]

In this letter, a compact circularly polarized (CP) multimode antenna for global navigation satellite system reflectometry (GNSS-R) is presented. The design comprises two quadrifilar helical antennas (QHAs), each fed with a ground coplanar waveguide (GCPW) and quarter wavelength power divider (QWPD) integrated feed. A hybrid staircase-shaped (SSR) QHA radial is proposed, and it is formed by serially arranging several vertical and diagonal elements. The electric field lines from the vertical elements converge constructively to radiate with the axis normal. Besides, the circular spatial offsets between the adjacent diagonal and vertical elements induce a 90 $^{\circ }$ delay in the field radiated. This hybrid shape launches an unprecedented theory facilitating normal mode of operation (MOOp) in QHA and generates CP over broad elevations and azimuths (0 $^{\circ }$ $< $ $\theta$ $< 80^{\circ }$ and 0 $^{\circ }$ $< $ $\phi$ $< 360^{\circ }$). Besides, the port-to-port 90 $^{\circ }$ spatial offset and the GCPW architecture yield high isolation ($>$ 20 dB). Unlike conventional GNSS-R antennas, this compact (170.5 mm × 132 mm) configuration operates in axial and normal mode, offers a broad beam coverage (237 $^{\circ }$), minimizes pattern interference between the two QHAs upon gap-free stacking, and ensures high delay accuracy in the remote sensing data computed. Additionally, it supports proficient (efficiency $>$ 0.9) multiconstellation remote sensing. The design prototype was fabricated and measured, and the measurements agreed well with the simulations. [ABSTRACT FROM AUTHOR]

This brief presents an 8-GHz Octa-phase Error Corrector (OEC) employing a digital delay-locked loop (DLL) with a coprime phase comparison scheme. To alleviate timing constraint during the phase comparison, clock phases spaced in coprime to 8 is utilized, enabling up to a 64-Gb/s link operation. In particular, this brief applies 3T/8 spaced clock rather than T/8. In addition, by employing a clock-divided 5-bit selection scheme, a high-speed 8:2 multiplexer (MUX) operates seamlessly without glitches. To minimize a mismatch and calibration -induced jitter, a single shared phase comparator and a finite-state machine (FSM) for tracking the minimum total delay are employed. The test chip has been fabricated in the 40-nm CMOS technology in an active area of 0.0814 mm2. The core phase calibration loop consumes 10.8 mW at 8 GHz at a 0.9-V supply achieving a maximum residue phase error of 0.95 ps. [ABSTRACT FROM AUTHOR]

This brief presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input–output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input–output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from $\boldsymbol{\pi }$ /2 to $\boldsymbol{\pi }$ /4. The resolution of the PR-DLL is 7-b of $2\boldsymbol{\pi }$ , which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%. [ABSTRACT FROM AUTHOR]

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx–Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, $640\times480$ imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed. [ABSTRACT FROM AUTHOR]

The nanosecond pulse generator, which works continuously at megahertz repetition rate, plays an important role in high-energy accelerators, electromagnetic biological effects, pulse laser modulation, and other fields. However, due to its own frequency limitation, a single SiC MOSFET switch cannot reach the required frequency. The use of multichannel MOSFET will make the drive control become more complex, thus facing more serious electromagnetic interference at high frequency. In this article, the method of pulse superposition is used to realize the output of megahertz pulse. At the same time, a delay driving circuit applied to the megahertz pulsed power supply is proposed. This solid-state hardware delay is carried out by using the deep saturation principle of the transistor, and multiple switches can be driven by only one signal. To verify its working principle, the experimental prototype is built which is composed of two modules. A single module contains two switches in parallel to achieve frequency superposition. Two modules are connected in series to increase the output voltage. The results show that the circuit can work stably at 1-MHz frequency. The repetitive pulse output with amplitude of 1.5 kV and pulsewidth of 320 ns can be obtained on the resistive load. Adding a truncated signal under a capacitive load, it can also achieve a voltage output with frequency of 1 MHz. [ABSTRACT FROM AUTHOR]

A new type of reconfigurable negative group delay (NGD) circuits based on active transversal filter topology is introduced in this work. By incorporating varactors with the NGD circuit at the input and output ports of active transversal filter based on distributed amplifiers (DAs), one can notably enhance the tunability for both amplitude and phase responses, thereby enabling NGD characteristic synthesis with a wider reconfigurable range. In this article, the proposed reconfigurable NGD circuits are applied to create both tunable non-Foster elements and tunable squint-free beamforming networks, which are verified by experiment. Furthermore, a general $N$ -stage transfer function for the proposed reconfigurable NGD circuit is derived, in which a two-stage particular case is given as an illustrative proof-of-concept example. Based on the reconfigurable NGD circuits, a prototype of a tunable negative capacitor is fabricated and measured, of which the capacitance can be tuned from −1.0 to −4.0 pF over a bandwidth of 100 MHz at 1 GHz or around 10% relative bandwidth. In addition, such an NGD circuit is utilized to create a low-dispersion superluminal transmission line, which enables a reconfigurable series antenna feedline for squint-free beam steering. Experimental results show that the main beam of the NGD antenna array has a tuning range from −15° to 15° within a squint-free bandwidth of 100 MHz at 2 GHz or within a relative bandwidth of around 5%. [ABSTRACT FROM AUTHOR]

In actual microgrids (MGs) networks, the information exchange between distributed energy resources (DERs) agents may be subject to various types of measurement noises and effected by communication time delays. This article proposes a resilient distributed multiagent control scheme for ac MG networks subject to additive noise and time-delay disturbances. The proposed multiagent control scheme is composed of three distributed consensus protocols, which is able to synchronize the output voltages and frequencies of inverter-based DERs to their reference values and achieve the optimal active power-sharing property by a low bandwidth communication network with noise and time-delay disturbances in almost sure convergence. By means of the stochastic analysis tools and algebraic graph theory, distributed consensus control protocols are designed to be employed for the secondary control level of MGs. On this basis, we deduce the stability criteria of the closed-loop MG system under noise and time-delay disturbances. As a result, the proposed consensus protocols can well restore the voltage and frequency’s derivation produced at the primary control level, meanwhile, can well achieve the optimal power sharing even though there exist communication disturbances. Several simulation scenarios on an islanded MG network are provided to verify the proposed control protocols’ performance. [ABSTRACT FROM AUTHOR]

In this letter, we study the joint device activity and delay detection problem in asynchronous massive machine-type communications (mMTC), where all active devices asynchronously transmit their preassigned preamble sequences to the base station (BS) for device identification and delay detection. We first formulate this joint detection problem as a maximum likelihood estimation problem, which depends on the received signal only through its sample covariance, and then propose efficient coordinate descent type of algorithms to solve the formulated problem. Our proposed covariance-based approach is sharply different from the existing compressed sensing (CS) approach for the same problem. Numerical results show that our proposed covariance-based approach significantly outperforms the CS approach in terms of the detection performance since our proposed approach can make better use of the BS antennas than the CS approach. [ABSTRACT FROM AUTHOR]

This work reports a comparative study of acoustic loss between different Lamb waves at GHz in thin-film lithium niobate (LiNbO3). The propagation loss (PL) of higher-order Lamb waves in thin-film LiNbO3 is studied for the first time using acoustic delay line (ADL) testbeds. The acoustic wave attenuation and quality factors ($Q$) of different Lamb waves are extracted, showing higher $Q\text{s}$ for higher-order Lamb modes than fundamental modes in air and vacuum at room temperature. The extracted $Q\text{s}$ are higher than those reported in thin-film LiNbO3 resonators, implying the electrode and anchor-induced loss as the dominant loss factors. The ADL-based loss analysis framework is readily extendable to acoustic damping study in other microwave acoustic platforms. [2021-0165] [ABSTRACT FROM AUTHOR]

The use of very high-resolution digital pulse width modulators (DPWMs) for high frequency dc–dc converters has been steadily increasing in recent years. However, the resolution of the DPWM formed by counters and comparators is limited when the switching frequency rise above MHz range. Given this limitation, new strategies for DPWM architectures are being designed to increase the resolution of the signals. This article proposes two new DPWMs architectures with the aim of increasing the resolution of trigger signals using field programmable gate arrays (FPGAs). The first proposed architecture is a hybrid DPWM, which integrates a clock manager and a delay line. For this architecture, the delay line is configured using FPGA intellectual properties (IP) blocks. This delay stage allows a fine resolution in the picosecond scale. In addition, an alternative solution has been implemented to generate two signals, the main signal and its complementary one, including high resolution for the dead time, which is also configurable. Both architectures have been tested through static and dynamic tests on two FPGAs of different costs, an Artix-7 (low-cost) and a Kintex-UltraScale 7 (high-cost) by Xilinx. [ABSTRACT FROM AUTHOR]

An ultrawideband (UWB) transmitarray antenna (TA) using receiving–transmitting scheme is presented in this letter. The TA overcomes its narrowband limitations by combining UWB radiators and integrated grounded coplanar transmission polylines. To reduce the manufacturing cost and the assembly complexities, all metallic components of the TA element are printed on a vertically oriented single-layer substrate, leading to a lightweight and solderless slat structure. The proposed TA element achieves true-time-delay phase responses over a fractional bandwidth of 116%, i.e., from 4.2 to 15.8 GHz, with maximum transmission loss of 1.6 dB at normal incidence. The dimensions of the designed 21 × 21 element TA aperture are 189 × 189 × 28 mm3, corresponding to 10 × 10 × 1.47λh3, where λh is the free-space wavelength at the highest operating frequency. A prototype is manufactured and measured to validate the feasibility. The experimental results agree reasonably well with simulations. [ABSTRACT FROM AUTHOR]

A uniplanar microstrip line RF/microwave real-time analog signal processing (RAP) units are proposed in this article to operate concurrently at two frequencies for spectrum aggregation applications. First, a fundamental building block novel microstrip line dual-band Hilbert transformer (DBHT) is developed by integrating a dual-band 180° coupler and a dual-band delay line (DBD). The theoretical analysis is carried out to determine the relation of coupler and delay line forming closed loop resonance in the proposed circuit topology. Then, a dual-band edge detector from DBHT and a dual-band single-sideband (DBSSB) modulator composed of dual-band power divider/combiner (DBPD/DBPC), DBHT, and DBD are developed for dual-band real-time RF/microwave signal processing. To verify the proposed concept, a prototype of microstrip line DBHT working at 0.9 and 1.98 GHz is designed, and the measurement and simulation agree well with theoretical analysis. To demonstrate the real-time RF/microwave analog signal processing, a dual-band edge detector composed of DBHT is verified in the experiment. Furthermore, a prototype of microstrip line DBSSB modulator is fabricated and validated in the experiment to demonstrate the real-time single-sideband modulation at two concurrent RF/microwave frequencies. [ABSTRACT FROM AUTHOR]

The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous accelerator has 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W. [ABSTRACT FROM AUTHOR]

Hybrid switches are attracting increasing attention recently, due to their high efficiency and low cost. Normally, two separated gate drivers and driving signals are needed for the hybrid switch, which leads to more cost and more control complexity. A novel gate driver circuit for SiC+Si hybrid switches is proposed using single driving signal and single-gate driver in this article. Two simple resistance-capacitance (RC) delay circuits are used for generating different time-delays required by two different triggering patterns to provide more flexibility. The detailed operation principles, mathematical analysis, and the guidance for the selection of key components of the proposed circuit are provided. The merits of the proposed driver are: first, simple structure; second, low control complexity; third, more flexibility; and fourth, low cost. A 2-kW Silicon Carbide (SiC)-MOSFET+Si-insulated gate bipolar transistor (IGBT) hybrid switch buck converter is built to validate the proposed gate driver circuit. The analysis and experimental results match very well, which shows the effectiveness and merits of the proposed method. [ABSTRACT FROM AUTHOR]

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 $\mu \text {m} \times 234\,\,\mu \text{m}$. The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°. [ABSTRACT FROM AUTHOR]

In a mobile edge computing (MEC) network, mobile devices, also called edge clients, offload their computations to multiple edge servers that provide additional computing resources. Since the edge servers are placed at the network edge, e.g., cell-phone towers, transmission delays between edge servers and edge clients are shorter compared to those of cloud computing. In addition, edge clients can offload their tasks to other nearby edge clients with available computing resources by exploiting the Fog Computing (FC) paradigm. A major challenge in MEC and FC networks is to assign the tasks from edge clients to edge servers, as well as to other edge clients, in such a way that their tasks are completed with minimum energy consumption and minimum processing delay. In this paper, we model task offloading in MEC as a constrained multi-objective optimization problem (CMOP) that minimizes both the energy consumption and task processing delay of the mobile devices. To solve the CMOP, we design an evolutionary algorithm that can efficiently find a representative sample of the best trade-offs between energy consumption and task processing delay, i.e., the Pareto-optimal front. Compared to existing approaches for task offloading in MEC, we see that our approach finds offloading decisions with lower energy consumption and task processing delay. [ABSTRACT FROM AUTHOR]

In this article, we introduce an improved multi-sampling-based alternate current (ac) controller that can be applied to ac machine drives or grid-connected inverters. Unlike the classical multi-sampling controller, whose performance is restricted by the transport delays in the feedback acquisition chain, the improved internal model control-based controller can provide a high closed-loop bandwidth by shortening the averaging range and inserting a cascaded differential multiplier. The corresponding modified controller structure for embedding active resistance feedback could improve the disturbance rejection ability while maintaining unchanged closed-loop performance for tracking reference. Besides the common perspectives for current controller design, discussions about robustness to parameter variations, implementation issue concerning sampling noise immunity affected by the pulse-width modulation output method, the effect of execution time, and application with high fundamental frequency are also presented. Finally, the comprehensive experimental results are obtained from a platform with a three-phase inverter, digital controller, and a surface-mounted permanent magnet synchronous motor. The results verify that the proposed controller achieves a high closed-loop bandwidth of up to 20% of the sampling frequency without overshoots and oscillations. [ABSTRACT FROM AUTHOR]

This work reports an experimental study of acoustic loss in thin-film lithium niobate (LiNbO3) using acoustic delay lines (ADLs). Unlike prior resonator-based quality factor (Q) studies, this approach directly extracts the damping in thin-film LiNbO3, avoiding the influence of other intricate loss mechanisms, e.g., anchor loss and electrode-induced loss. Acoustic attenuation of fundamental symmetric (S0) and shear horizontal (SH0) waves are studied in suspended LiNbO3 thin films of different thicknesses. The attenuation is significantly higher in thinner LiNbO3 films, suggesting the LiNbO3 crystal degradation during the microfabrication as the primary loss origin. Nevertheless, the extracted equivalent Q in thin-film LiNbO3 is still higher than reported values, suggesting that anchor design and electrode quality remain the bottlenecks for higher Q. The proposed loss extraction framework is readily extendable to other acoustic thin-film structures. [2021-0107] [ABSTRACT FROM AUTHOR]

Microstrip ultra-wide band (UWB) delay lines consisting of a novel periodically loaded transmission line (PLTL) are presented, along with discontinuous structured guard lines (DSGLs). The distinctive advantage of the proposed approach is that the far-end crosstalk (FEXT) between the adjacent lines is effectively suppressed comparing to the conventional circuits. Afterward, the crosstalk of connected adjacent lines is effectively suppressed by modifying the DSGLs, since the current distributions are different from the separated adjacent lines. Subsequently, the strong reflection points are eliminated, which seriously deteriorate the performances in amplitude and group delay. Moreover, the serpentine delay line (SDL) and serpentine meandered delay line (SMDL) are studied, respectively, using the conventional microstrip (CMS) and the proposed PLTL with DSGLs. As a result, the SMDL pattern is also demonstrated useful to suppress the near-end crosstalk (NEXT) between the adjacent second-level curves, which in turn reduce the fluctuations in the group delay. In addition, the PLTL SMDL with DSGLs consequently have the superiority of suppressing the NEXT and FEXT simultaneously. Further simulations and measurements indicate that the performances of the PLTL SMDL with DSGLs lines are superior to the conventional method in a UWB range of dc to 25 GHz, including amplitude and group delay flatness, along with high time delay efficiency due to the slow wave property. [ABSTRACT FROM AUTHOR]

In the Cooling storage ring External-target Experiment (CEE) in heavy ion research facility in Lanzhou (HIRFL), multigap resistive plate chambers (MRPCs) detectors are used for high-precision time-of-flight (TOF) measurement to identify the scattered particles after the ion beam hits the target. Regarding the external TOF (eTOF) and 2/3 internal TOF (iTOF) detectors, a ~25-ps rms time precision is required for the readout electronics, whereas for the other 1/3 iTOF detectors, a ~10-ps rms precision is required. A readout electronics prototype was designed, including the front-end electronics (FEE) based on analog signal amplification, discrimination, and the time-to-digital module (TDM), based on field-programmable gate array (FPGA) time-to-digital converter (TDC), to achieve high-precision time measurement. PreAmplifier-DIscriminator (PADI) is used in the design of the FEE, while an FPGA TDC, based on tapped delay line (TDL) structure, with a time precision performance better than 5-ps rms, is implemented in the TDM, as well as the trigger matching circuit and other control logic. The performance of the whole system was tested under different input signal charges and the results indicated that the time precision is better than 10-ps rms, which satisfies the application requirements. [ABSTRACT FROM AUTHOR]

We present the design and test results of a time-to-digital-converter (TDC). The TDC will be a part of the readout Application-Specific Integrated Circuit (ASIC), called endcap timing read-out chip (ETROC), to read out low-gain avalanche detectors (LGADs) for the CMS endcap timing layer (ETL) of high-luminosity large hadron collider (LHC) upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 $\mu \text{W}$ for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the time of arrival (TOA) and the time over threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65-nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 and 9.9 ps with and without nonlinearity correction, respectively. The TDC block consumes 97 $\mu \text{W}$ at the hit occupancy of 1%. Over a temperature range from 23 °C to 78 °C and a power supply voltage range from 1.05 to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation tolerance specifications. [ABSTRACT FROM AUTHOR]

This article presents a high linearity time-to-digital converter (TDC) with tunable parameters, based on a field-programmable gate array (FPGA) device. Specifically, a nonuniform monotonic multiphase (NUMMP) method is proposed to reestablish equivalent delay units with nonuniform delay time to overcome the limitation of the intrinsic delay and the uniformity of delay element in FPGA first. Then, the raw data frame composed of the equivalent delay units is marked by a time scale marking (TSM) method. Third, a feature extraction (FE) method is proposed to extract the marked raw data frame to form a feature frame, which can reduce the data volume by 79.1%. After that, the feature frames are decoded by a proposed coarse-fine decoding (CFD) algorithm, which can increase the decoding speed, shorten the dead time to 8 clock cycles and reduce the amount of decoding calculation by 80%. Finally, the proposed TDC has been verified with a Xilinx Kintex-7 FPGA. The measurement results demonstrate that the proposed NUMMP TDC with highly adjustable linearity and resolution has been realized. For a high linearity configuration with an LSB of 20 ps, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are only +0.06/−0.05 and +0.08/−0.15 LSB, respectively. And for a high-resolution configuration with an LSB of 1.87 ps, the root mean square (rms) for the resolution can achieve 2.79 ps, and the values of the DNL and INL are +1.30/−0.54 and +3.51/−2.21 LSB, respectively. [ABSTRACT FROM AUTHOR]

This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs). Channels of that TDC are mainly composed of look-up Tables (LUTs) configured as embedded memories. The channels share the same ring oscillator. A previously proposed delay tuning method was used to increase the overall accuracy by balancing the TDC channels. Compared to previously reported TDCs, the proposed architecture consumes fewer resources without degrading performances. A nine-channel TDC was implemented in a Zynq-7 Xilinx FPGA. Single-shot precision of 92.7 ps and accuracy of 92.9 ps were achieved, while consuming 1.49% and 1.31% of the available LUTs and FFs of a ZYNQxc7z010-3clg400 Xilinx FPGA, respectively. [ABSTRACT FROM AUTHOR]

Measurement of optical transfer delay (OTD) is crucial to applications such as fiber-distributed multiantenna systems, fiber-optic sensors, and high-capacity optical fiber communications. However, present OTD measurement techniques are inadequate for the demands of high accuracy, high speed, and large measurement range, simultaneously. Here, we propose a novel method based on nonlinear frequency sweeping and phase derived ranging to achieve all the above-mentioned performance. A continuous-wave light modulated by a microwave signal propagates in a device under test. Then, the OTD is mapped into the phase variation of the microwave signal by photodetection. A microwave phase discriminator is used to extract the phase variation from the microwave signal, while the nonlinear frequency sweeping and a novel phase unwrapping algorithm are proposed to resolve $2\pi $ phase ambiguity caused by phase detection. Frequencies of the microwave swept signals are set at four selected points in a range of 10 MHz, which ensures high speed and large measurement range. Our experiment results verify an accuracy of ±0.05 ps in measuring an ultrahigh-accuracy optical delay line. In addition, long fiber is also tested, which proves that a measurement range of at least 37 km (theoretically 100 km) can be achieved. Moreover, the measurement speed reaches milliseconds per measurement. [ABSTRACT FROM AUTHOR]

The increase of within-die random variation accompanying continuing advancement of the semiconductor technology necessitates variation-aware approaches in circuit design and analysis. Statistical circuit modeling becomes an important means of realizing such approaches. In this article, analytical models for the within-die random variation of the inverter, NAND and NOR circuits are developed. To analyze random variation, the effective current concept is employed wherein circuit delay is approximated by the product of the load capacitance and supply voltage over two times the effective current. The standard deviation and mean of the circuit delay are expressed as functions of the standard deviation and mean of the effective and linear transistor currents. The developed model delivers easy means of evaluating delay variation of basic circuits. The model is verified by comparison to Monte-Carlo circuit simulations for 7-nm state-of-the-art FINFET technology. Relative error for NAND2 fall/NOR2 rise mean delay is less than 9% and for standard deviation is less than 6%. Relative error for inverter rise/fall mean delay is within 8%, however, error is larger for inverter delay standard deviation. The model is convenient for analyzing the dependence of the circuit delay standard deviation on the transistor width and the supply voltage and is useful for improving technology development efficiency in achieving target circuit performance. [ABSTRACT FROM AUTHOR]