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In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu-polishing process. First, a bulk of Cu is removed with the slurry of high Cu removal rate and second, the Cu surface is planarized with the slurry of high Cu passivation capability. The Cu dishing can be improved up to 97% for the 10-\mum-diameter TSVs on a 300-mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly optimized Cu-plating overburden for TSVs and redistribution layers. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a larger TSV diameter still keep in a plateau-like shape after CMP. [ABSTRACT FROM AUTHOR]

Thermal performance of 3D IC integration is investigated in this study. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, the thermal behavior of a TSV cell is examined. Furthermore, 3D heat transfer simulations are adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure. [ABSTRACT FROM AUTHOR]

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 \mum in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 \mum in diameter and 25 \mum in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs. [ABSTRACT FROM PUBLISHER]

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21\,\times\,21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-\mum SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25\,\times\,25\,\times\,0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45\,\times\,45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements. [ABSTRACT FROM PUBLISHER]

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-k materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 \mum) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (-40^\circC to 125^\circC) and high temperature storage (HTS at 150^\circC) for 1000 h. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic underfill selection and characterization methods for 21\,\times\,21 mm^2 Cu/low-K flip chip packages (65 nm technology) with 150 \mum bump pitch. This paper has also correlated the underfill characterization methods with the reliability results of 15\,\times\,15 mm^2 and 21\,\times\,21 mm^2 Cu/low-K flip chip packages. From the validations of underfill selection and characterization approach with the reliability of 21\,\times\,21 mm^2 Cu/low-K flip chip package, it was found that the reliability results correlated well with the adhesion test results. Underfill/flux compatibility and underfill flow performance are found to be important factors during underfill selection. Underfill should not be sieved out at the initial stage without actual reliability tests. [ABSTRACT FROM PUBLISHER]

Copper(Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm x 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-µm pitch in two depopulated rows using redistribution layers (RDL).Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 µm height with SnAg solder cap and SnAg solder bump of 150 µm height with 5-µm-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow under fills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-kWLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL. [ABSTRACT FROM AUTHOR]

Low-temperature hermetic wafer bonding using In/Sn interlayer and Cu/Ti/Au metallization was investigated for microelectromechanical systems packaging application. In this case, the thin Ti layer was used as a buffer layer to prevent the diffusion between solder interlayer and Cu after deposition and to save more solders for diffusion bonding process. Bonding was performed in a wafer bonder at 180 and 150 °C for 20 mm with a pressure of 5.5 MPa. It was found that bonding at 180 °C voids free seal joints composed of high-temperature intermetallic compounds were obtained with good hermeticity. However, with bonding at 150 °C, voids were generated along the seal joint, which caused poor hermeticity compared with that bonded at 180 °C. After four types of reliability tests--pressure cooker test, high humidity storage, high-temperature storage, and temperature cycling test--dies bonded at 180 °C showed good reliability properties evidenced by hermeticity test and shear tests. Results presented here prove that high-yield and low-temperature hermetic bonding using Sn/In/Cu metallization with thin Ti buffer layer can be achieved. [ABSTRACT FROM AUTHOR]

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 × 10-6/°C) is a few times higher than that of silicon (~2.5 × 10-6/°C). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 × 10-6/° C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps. [ABSTRACT FROM AUTHOR]

Abstract: This paper reports the design, assembly and reliability assessment of 21×21mm2 Cu/low-k flip chip (65nm node) with 150μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL. By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations. [Copyright &y& Elsevier]