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This work presents a novel process to manufacture advanced Germanium-On-Insulator with integrated Silicon Nitride (GOIN) stripes as light waveguide for Ge photonic devices. Through the integration of GOIN stripes, larger tensile strain could be imposed to the bonded Ge layer which may could be used to tailor the bandgap of Ge material for short wave length infrared application. The successful fabrication of advanced GOIN substrate makes the opportunity for monolithic integration of high-performance Ge-based high mobility transistors with photonic components where silicon nitride is the waveguide with low optical loss.

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift ( ${\Delta }$ V $_{T}$ ), pre-existing traps ( ${\Delta } {N} _{\mathrm {HT}}$ ), generated traps, and their relative contributions were studied. The time exponents of ${\Delta }$ V $_{T}$ , the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ${\Delta }$ V $_{T}$ , and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ${\Delta } {N} _{\mathrm {HT}}$ is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

This work presents a novel process to form SiNx films and process for membranes with excellent mechanical properties for micro-electro-mechanical systems application as well as integration as IR waveguide for photonic application. The SiNx films were fabricated in SiNgen apparatus which is a single wafer chamber equipment compared to conventional low pressure chemical vapor deposition furnace process. The films showed low stress, good mechanical properties, but the synthesis also eradicates the issues of particle contamination. Through optimizing of the growth parameters and post annealing profile, low stress (40 Mpa) SiNx film could be finally deposited when annealing temperature rose up to 1150 °C. The stress relaxation is a result of more Si nano-crystalline which was formed during annealing, according to the FTIR results. The mechanical properties, Young’s modulus and hardness, were 210 Gpa and 20 Gpa respectively. For the waveguide application, a stack of three layers, SiO2/SiNx/SiO2 was formed where the optimized layer thicknesses were used for minimum optical loss according to simulation feedback. After deposition of the first two layers in the stack, the samples were annealed in range of 900–1150 °C in order to release the stress. Chemical mechanical polish technique was applied to planarize the nitride layer prior to the oxide cladding layer. Such wafers can be used to bond to Si or Ge to manufacture advanced substrates.

Embedded fin in phase change materials (PCMs) is one of the most efficient methods to enhance the heat transfer between the PCM and heat transfer fluid (HTF). An appropriate arrangement of the fins plays significant role to design a highly efficient latent heat thermal energy storage (LHTES) unit. The aim of this study is to find the most efficient arrangement of fins to accelerate the charging rate. A two-dimensional numerical model based on finite volume method (FVM) was developed with considering natural convection and the calculation results were validated with experimental data. The heat transfer characteristics of LHTES unit with different fins arrangements were firstly explored. These include no fins, straight fins, angled fins, lower fins and upper fins. Then, the effects of fins number (N), dimensionless fins length (l), heat transfer fluid temperature (Tw) and outer tube material on melting performance for four arrangements were studied. In addition, the best type of arrangements to increase the efficiency of heat exchanger was suggested. The performance enhancement of LHTES through fins configuration were quantitatively described based on complete melting time and heat storage capacity, and the conclusions are arrived as follows: when N ≤ 6, the optimum arrangement is the lower fins, while it is the angled fins when N > 6. For N = 6, only l could change the optimum arrangement of fins. At l equals 0.5 and 0.95, the optimum arrangement is angled case. While at l = 0.75, the optimum arrangement is lower case. It is also found that the heat storage capacity of lower fins configuration is minimal compared to other three configurations.

We experimentally investigate the effect of post-deposition annealing on the charge distribution of a metal-oxide-semiconductor capacitor with a TiN/HfO2/SiO2/Si gate structure. We decoupled interfacial charges at the SiO2/Si and HfO2/SiO2 interfaces; bulk charges in HfO2; and the dipole formation at the HfO2/SiO2 interface. The interfacial charges at the HfO2/SiO2 interface decreased and the dipole increased after H2 or N2 annealing. Oxygen dangling bonds are the physical origin of the charges at the HfO2/SiO2 interface. The interfacial charges at the SiO2/Si interface and the bulk charges in HfO2 are almost unchanged.

The effects of sintering parameters and microstructure features on magnetic properties of Fe-3 wt.% Si alloy prepared by metal injection molding (MIM) was investigated in this study. The sample with high density, the saturation induction (Bs) of 2.0 T, maximum permeability (μmax) of 25 mH/m, coercivity of 22.4 A/m was obtained at 1300 °C for 4 h in hydrogen atmosphere, and the properties of which are close to that of high silicon steel. The microstructure, impurities of C and O, distribution of grain boundary angles and magnetic domain of the sintered alloys were analyzed in correlation with the magnetic properties. It is found that a suitable large grain size of about 300 μm and large grain boundary angles distributed in the range of 30°–60° are beneficial to soft magnetic properties. Moreover, uniform and broad magnetic domains also play an important role in preparation of high performance soft magnetic materials.

A pre-ohmic micro-patterned recess process, is utilized to fabricate Ti/Al/Ti/TiN ohmic contact to an ultrathin-barrier (UTB) AlGaN/GaN heterostructure, featuring a significantly reduced ohmic contact resistivity of 0.56 Ω·mm at an alloy temperature of 550 °C. The sheet resistances increase with the temperature following a power law with the index of +2.58, while the specific contact resistivity decreases with the temperature. The contact mechanism can be well described by thermionic field emission (TFE). The extracted Schottky barrier height and electron concentration are 0.31 eV and 5.52 × 1018 cm−3, which suggests an intimate contact between ohmic metal and the UTB-AlGaN as well as GaN buffer. A good correlation between ohmic transfer length and the micro-pattern size is revealed, though in-depth investigation is needed. A preliminary CMOS-process-compatible metal–insulator–semiconductor high-mobility transistor (MIS-HEMT) was fabricated with the proposed Au-free ohmic contact technique.

We use fast characterization methods to study DC and AC negative bias temperature instability (NBTI) kinetics in pMOSFETs with varying TiN capping layer thickness (tTiN). The effects of tTiN scaling on the threshold voltage shift (ΔV t ), pre-existing hole traps, and generated traps (ΔN t ) and their relative contribution are characterized. The time exponents of ΔV t and ΔN t and the effects of stress bias, temperature, frequency, and duty cycle on the degradation are analyzed. Devices with lower tTiN show reduced DC and AC NBTI, and a lifetime improvement of 60% is realized when tTiN is scaled down from 3 to 1 nm. We experimentally confirm that bulk trap generation (ΔN ot ) is an f-dependent subcomponent and that its relative contribution in ΔV t reduces with lower tTiN, which is the main reason for the improvement in NBTI through tTiN scaling.

Silicon nitride (SiNx) grown by low-pressure chemical vapor deposition (LPCVD) at a reduced growth temperature (650 °C), is utilized for fabrication of GaN metal–insulator-semiconductor (MIS) power devices. An atomically sharp interface between the LPCVD-SiNx and GaN was achieved, featuring a disordered region with only a thickness of 2.5 ~ 5 A. A fabricated LPCVD-SiNx/GaN/AlGaN/GaN MIS diode exhibits a sharp two-step capacitance–voltage behavior with small frequency dispersion of 0.4 V in the right step. The improved interface was quantified by a well-elaborated constant-capacitance deep-level transient Fourier spectroscopy (CC-DLTFS), delivering quite low density of 1.5 × 10 13 cm - 2 eV - 1 at the level depth of 30 meV and about 4 × 10 11 ~ 1.2 × 10 12 cm - 2 eV - 1 at the level depth of 1 eV. Distributions of interface states can be described by a proposed physics-based decoupling function featuring an exponential law. A discrete level at the SiNx/GaN border or in the barrier layer with the level depth and the capture cross section being 0.8 eV and 5.5 × 10 - 14 cm 2 respectively, can thus be detached from the interface states.

A comparative study on negative bias temperature instability (NBTI) is carried out in replacement metal gate Si p-FinFETs featuring atomic layer deposition (ALD) tungsten (W) filling metal using B2H6 and SiH4 precursors. A fast measurement technique is used to characterize the threshold voltage shift (ΔVT). The effect of ALD W filling metal process on ΔVT, generated interface traps (ΔNIT), pre-existing hole traps (ΔNHT), stress voltage, and temperature dependence of degradation is demonstrated. Comparing with their B2H6-based counterpart, SiH4-based devices show reduced ΔVT under identical stress conditions due to reduced ΔNHT and ΔNIT. SiH4-based devices exhibit a 1.5 times higher fluorine content at the interfaces and larger compressive strain in the channel than B2H6-based devices, which are found to be responsible for the reduced ΔNIT. A modeling framework is proposed to model the long-term time evolution of NBTI degradation, and the predicted maximum overdrive voltage is compared. SiH4-based devices exhibit superior reliability and a 20% improvement in the maximum operation overdrive voltage than B2H6-based devices, and can be implemented in the advanced CMOS technology.

Silicon nitride (SiNx) film grown by low-pressure chemical vapor deposition (LPCVD) is utilized as a gate dielectric for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Trap distribution at the gate-dielectric/III-nitrides interface is characterized by a temperature-dependent ac-capacitance technique. The extracted interface state density D it decreases from 2.92 × 1013 to 1.59 × 1012 cm−2 eV−1 as the energy level depth (E C-E T) increases from 0.29 to 0.50 eV, and then levels off to E C-E T = 0.80 eV. Capacitance-mode deep level transient spectroscopy (C-DLTS) and energy band diagram simulations reveal that deep levels with E C-E T > 0. 83 eV are responsible for the dispersion of capacitances at high temperature (>125 °C) and low frequencies (