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An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

This paper proposes a complete and full automation framework of evaluating design rules (DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly demanded in 14-nm and beyond technologies. Our proposed framework explores the changes of DRs and evaluates the impacts on the number and types of DR violations as well as the resulting cell/chip layout area. Precisely, the core engine of our DR evaluation framework for DTCO, the automatic cell layout generator, consists of key enabling techniques for standard cell layout optimization. They are integrated coherently to seamlessly support the advanced process technologies using FinFET transistors, complex DRs, and double patterning (DP) lithography. Also, the tight integration of our automatic cell layout generation into the DR evaluation framework with diverse analysis features enables the DTCO process to be much faster and more efficient. We provide a set of experimental data not only to show how much our proposed enabling techniques are effective in optimizing layouts but also to show how effectively our framework explores and analyzes the DTCO parameters (e.g., ground DRs and DP DRs).

A 28nm embedded Flash memory in this paper is designed for the Automotive application in Foundry. Through Temperature Auto-Tracking Sense Amplifier using the Bit line Charge Boost (BCB) and Bit line Leakage current Compensation (BLC) technology, it succeeded in implementing under 10ns read operation (>100MHz) and size improvement (7.42Mb/mm2). Also Word Line and YMUX Gate Boost (WYGB) is applied to secure a sensing margin at a low voltage (0.85V). These techniques enable 10ns reading operation of 288 bits (26.8Gb/s) at a time based on 16Mb memory size by improving sensing margin in temperature range of -40~150’C. It also implemented a competitive minimum IP size and we have secured high yield that enough to mass production as a result of Silicon validation. Based on competitive advantage through technology differentiation, it will be provided to various customers in all eFlash IP Foundry markets including Automotive business.

Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-ability. A 5nm EUV FinFET test chip demonstrates 210mV VMIN improvement and 4.7x larger range of operating voltage with VACPL. The proposed VACPL and VATA achieves 95.2% leakage power reduction by lowering VDDC by 400mV in 5nm 5G mobile device.

This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.

Advanced technologies help to improve SRAM performance via recent transistor breakthroughs [1], which allow SRAM designers to focus on handling metal resistance by alleviating device performance impediments. Since SRAM margins are more vulnerable to the increasing metal resistance, due to smaller critical dimensions, SRAM-assist circuits are proposed to overcome the impact of metal resistance in recent technologies [2 –5]. One of the challenges is the design limitation such as the quantized transistor, which requires SRAM-assist to optimize SRAM margins. In this paper, gate-all-around (GAA) SRAM design techniques are proposed, which improve SRAM margins more freely, in addition to power, performance, and area (PPA). Moreover, SRAM-assist schemes are proposed to overcome metal resistance, which maximizes the benefit of GAA devices.

Embedded SRAM is a key component that typically determines the overall processor performance. A fully customized SRAM requires a long design cycle; hence, an SRAM compiler that can provide a wide range of user-specified SRAM designs, by utilizing predefined leaf cells, is widely used. An SRAM compiler must exhibit robustness across a wide range of voltage and temperature conditions. On top of optimizing power and performance for a variety of applications, a compiler also enables dynamic voltage and frequency scaling. However, the temperature and voltage sensitivity of an SRAM bitcell limits its voltage and temperature operating range, thus significantly degrading read and write stability. Several approaches to improve SRAM stability have been proposed [1]–[6]; however, the WL under-drive (WLUD) read-assist technique is the most widely used: owing to its simple architecture, and smaller power and area overhead [12]. However, this approach reduces the WL voltage at voltage and temperature conditions that do not require WLUD; thus, degrading read speed and the write margin (WRM).

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85–5.88 times and 35%–70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.

In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.

11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.

Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.

In this paper, we have presented 28-nm embedded 8Mb 64 I/O Spin-Transfer-Torque Magnetic RAM (STT-MRAM) Macro. Besides being the one of the world's first mass product solution for embedded Flash (eFlash) replacement for Internet-of-Things (IoT) chips, it is also serves as a comprehensive storage memory solution in high-end System-on-Chip (SoC). The read and write cycle times are 20ns. Thanks to process and temperature compensated reference concept, the Macro gives a non-fail read at Magnetic Tunnel Junction (MTJ) RP and RAP resistances variation up to 1sigma 8% and at weak Tunnel Magnetic Resistance (TMR) down to 150%. Macro operates in industrial temperature range. The integrated adaptive Read-and-Write biasing circuit improves MTJ endurance and optimizes the memory's power consumption by 20%. The presented STT-MRAM saves 15 to 40% of area, compared to the same process eFlash.

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.

A low-power technique for a static random-access memory (SRAM)-based on-chip arbitrary-waveform generator (AWG) is proposed for two types of analog-signal-processing applications: multiresolution spectrum sensing and matched filter. The SRAM has an embedded address generator to limit the operation in a sequential-access mode of the AWG. Then, the power consumption of the AWG is analyzed according to the operation modes in multiresolution and multiwaveform spectrum-sensing functions. The low-power technique reduces power by 18% of the SRAM and the address generator and by about 2.2% of the entire AWG at a 1.8-V supply voltage. The AWG is fabricated in a 0.18-μm CMOS technology and demonstrates a chirp signal and a Daubechies wavelet with a 45-dBc spurious-free dynamic range and a cross-correlation factor of 0.96-0.988 with ideal signals.

The matrix determinant computation system (MDCS) is developed in subthreshold current-mode for an analog signal processing. By utilizing the translinear loop principle and the novel differential architecture, the MDCS can perform accurate addition, subtraction, and multiplication in analog domain. The system computes a 2-by-2 and 3-by-3 determinant with 91 % accuracy and a 3 kHz input can be handled while consuming 110.05μW. The overall system is fabricated on a 0.18μm CMOS technology and the area is 500μm × 800μm.

In this paper, a fully-integrated synchronizable AWG for radar pulse compression is presented. For low power operation, we suggested the two-layered x-decoder scheme which includes address increment circuits so that HOaddr buffers need not to be operated in generating the repetitive waveforms. This can save the power consumption of HOaddr buffer by about 9-18% depending on HOaddr toggling ratio. The measurement results using MRSS IC show the chirp signal and Daubechies waveforms successfully.

Cognitive radio (CR) technology has been proposed as a promising solution for maximizing the utilization of already-crowded spectrum resources. As new algorithms, circuits and systems are developed for CR technology, it is essential to have a reconfigurable testbed system for their verification. A multistandard, fully software driven, cross-layer CR testbed has been developed to support thorough testing of CR system and custom designed integrated circuits (ICs). This paper presents details of cross-layer CR testbed and three demonstrations of testbed usage; (a) cognitive radio system concept demonstration, (b) multi-resolution spectrum sensing (MRSS) receiver IC evaluation, (c) interference analysis for UWB coexistence with WiMax. With this reconfigurable testbed, a new idea can be easily verified, demonstrated and extended to further research.

Spectrum sensing is a key function for a Cognitive Radio (CR) system. An analog-based Multi-Resolution Spectrum Sensing (MRSS) technique was proposed as a flexible, low-power, high-speed spectrum-sensing solution. In this paper, implementation issues of the MRSS technique are investigated, and the corresponding practical specifications are suggested. First, nonlinear effects from a Voltage-Controlled Oscillator (VCO) and multipliers are explored. System simulation results show that harmonic distortion components of VCO and wavelet-pulse power levels should be controlled to alleviate these nonlinear effects. Afterward, I/Q phase- and gain-mismatch effects are addressed. Specifically, narrow-band signals are more sensitive to these gain and phase mismatches compared to broadband digital modulated signals. Overall, phase mismatch is more sensitive than gain mismatch on MRSS performance, showing a linear degradation of a detected power-level up to a 60-degree phase-mismatch.

A new dynamic comparator with enhanced input range is reported. Input trip point deviations from ideal values are shown to be less than a conventional comparator over a wide input range. This new dynamic comparator can be beneficial to low supply voltage analogue-to-digital converters (ADCs), especially to pipeline ADCs.