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Dedicated infrastructures are commonly used for urgent computations. However, using dedicated resources is not always affordable due to budget constraints. As a result, utilizing shared infrastructures becomes an alternative solution for urgent computations. Since the infrastructures are meant to serve many users, the urgent jobs may arrive when regular jobs are using the necessary resources. In such a case, it is necessary to preempt the regular jobs so that urgent jobs can be executed immediately. Most conventional methods for job scheduling have focused on reducing the response times and waiting times of all jobs. However, these methods can delay urgent jobs and hinder them from being completed within a stipulated deadline. Furthermore, in heterogeneous systems with coprocessors, preemption becomes more difficult because coprocessors rely on several system software functionalities provided by the host processor. In this paper, we propose a parallel job scheduling method to effectively use shared heterogeneous systems for urgent computations. Our method employs an in-memory process swapping mechanism to preempt jobs running on the coprocessor devices. The results of our simulations show that our method can achieve a significant reduction in the response time and slowdown of regular jobs without substantial delays of urgent jobs.

The mapping of tasks to processor cores, called task mapping, is crucial to achieving scalable performance on multicore processors. On modern NUMA (non-uniform memory access) systems, the memory congestion problem could degrade the performance more severely than the data locality problem because heavy congestion on shared caches and memory controllers could cause long latencies. Conventional work on task mapping mostly focuses on improving the locality of memory accesses. However, our previous work showed that on modern NUMA systems, maximizing the locality can degrade the performance due to memory congestion. In this work, we propose a task mapping method that addresses the locality and the memory congestion problems to improve the performance of parallel applications. In the proposed method, first, the spatial and temporal communication behaviors of the applications are analyzed from the time-series dataset of communications among the parallel tasks. Then, a data clustering technique is employed to detect groups of tasks that potentially cause the memory congestion. Finally, this information is used to compute the task mapping to improve the locality and reduce the memory congestion. We also provide a set of metrics to describe the communication behaviors and to evaluate if the target application can benefit from our method. The proposed method is evaluated with the NPB and PARSEC applications on a real NUMA system and a multicore simulator. A detailed analysis of the sources of performance gain is also provided. Experimental results show that our method can achieve up to a 61% performance improvement compared with the state-of-the-art locality-based method.

Recently, many researchers are investigating quantum annealing as a solver for real-world combinatorial optimization problems. However, due to the format of problems that quantum annealing solves and the structure of the physical annealer, these problems often require additional setup prior to solving. We study how these setup steps affect performance and provide insight into the interplay among them using the job-shop scheduling problem for our evaluation. We show that the empirical probability of success is highly sensitive to problem setup and that excess variables and large embeddings reduce performance. We then show that certain problem instances are unable to be solved without the use of additional post-processing methods. Finally, we investigate the effect of pausing during the anneal. Our results show that pausing within a certain time window can improve the probability of success, which is consistent with other work. However, we also show that the performance improvement due to pausing can be masked depending on properties of the embedding, and thus, special care must be taken for embedded problems.

Modern high-performance computing (HPC) systems consist of a large number of nodes featuring multi-core processors. Many computational fluid dynamics (CFD) codes utilize a Message Passing Interface (MPI) to exploit the potential of such systems. In general, the MPI communication costs increase as the number of MPI processes increases. In this paper, we discuss performance of the code in which a core is used as a dedicated communication core when the core cannot contribute to the performance improvement due to memory-bandwidth limitations. By using the dedicated communication core, the communication operations are overlapped with computation operations, thus enabling highly efficient computation by exploiting the limited memory bandwidth and idle cores. The performance evaluation shows that this code can hide the MPI communication times of 90% on the supercomputer SX-ACE system and 80% on the supercomputer SX-Aurora TSUBASA system, and the performance of the successive over-relaxation (SOR) method is improved by 32% on SX-ACE and 20% on SX-Aurora TSUBASA.

As the number of cores on a processor chip increases, the capacity and the number of levels of the cache hierarchy increases, which causes higher energy consumption of the computing system. However, the usage of a cache hierarchy may vary significantly among applications. Thus, determining an appropriate cache hierarchy for each application is crucial to improve performance and energy efficiency. In this paper, we propose a mechanism to improve energy efficiency by adapting a cache hierarchy to individual applications. First, our mechanism bypasses and disables some of the cache levels if their contributions to performance are small. Then, based on the cache utility, the mechanism optimizes the capacity and associativity of the last-level cache. The experimental results with the PARSEC benchmarks show that the proposed mechanism can improve energy efficiency by 26% and 10%, compared with the baseline and cache-level bypassing mechanisms, respectively.

This paper presents an extension of Kokkos for modern vector processors, such as Vector Engines of SX-Aurora TSUBASA (VEs). Kokkos is a C++ library that provides polymorphic memory access patterns, and widely used for keeping high performance portability of applications. Although Kokkos does not officially support VEs as of July 2020, VEs can execute standard C++ programs, and the original Kokkos can indeed be compiled for VEs. However, the memory access pattern provided by Kokkos for standard processors is not necessarily suited for VEs. For example, it is known that memory access conflicts could drastically degrade the sustained memory bandwidth on VEs, even though, for memory access conflicts, standard processors assumed in Kokkos, i.e., x86 processors, are less performance-sensitive than VEs. Therefore, we propose an extended Kokkos implementation for VEs, which can provide memory access patterns suited for VEs. Specifically, we mainly focus on avoiding memory access conflicts on VEs. This paper introduces a mechanism to automatically avoid memory access conflicts, and explains its implementation. We evaluate our proposal using some benchmark codes, and the results demonstrate that our proposal can successfully exploit the high memory bandwidth of VEs.

Although there are various ways of implementing sparse matrix vector multiplication (SpMV), there is no established way of predicting the best implementation for individual sparse matrices, and thus an SpMV implementation has empirically been selected for each matrix. Cui et al. have proposed a machine learning approach to the prediction. However, their approach focuses only on predicting the best implementation for each matrix, and does not consider the performance differences among candidate implementations. If the performance difference between the best and non-best implementations for a matrix is large, the performance loss by the misprediction is also large. Thus, a machine learning model needs to be trained to preferentially avoid misprediction of such a matrix to achieve a higher expected performance. Therefore, this paper presents a machine learning approach that considers the performance differences at the best SpMV implementation selection problem and quantitatively discusses the performance improvement by the approach. The evaluation results clearly demonstrate that the proposed approach can prevent a machine learning model from selecting significantly low-performance implementations, and thereby improve the expected performance in comparison with the previous approach.

NEC SX-series vector supercomputers have provided outstanding memory bandwidths to meet the strong demands for efficient execution of memory-intensive scientific applications in practice. Inheriting the advantage, the 2nd generation SX-Aurora TSUBASA, Type 20B, provides an extremely high memory bandwidth of 1.53 TB/s per vector processor. Unlike conventional SX-series systems, SX-Aurora TSUBASA also offers various execution modes to execute a diversity of emerging scientific workloads efficiently. As a result, application developers need to understand their workloads and the performance characteristics of SX-Aurora TSUBASA, and select an optimization strategy assuming an appropriate execution mode to fully exploit the system performance. Therefore, this paper discusses workload characterization by performance bottleneck analysis to determine an optimization strategy for the 2nd generation SX-Aurora TSUBASA. The evaluation results with benchmarks and real-world applications demonstrate that the workload characterization approach can accurately find the bottleneck and characterize various workloads, by helping application developers decide the optimization strategies for individual workloads. Since we can consider SX-Aurora TSUBASA as a typical example of the latest processors with high memory bandwidths, the workload characterization approach will also be helpful for other future processors.

This paper presents a method for automatically avoiding performance degradation due to memory access conflicts on Vector Engines (VEs) of NEC SX-Aurora TSUBASA. Although VEs have the world's top-class theoretical memory bandwidth, the sustained memory bandwidth is significantly decreased if frequent memory access conflicts occur. In order to fully utilize the potential memory bandwidth of VEs, programmers need to optimize codes manually to avoid the conflicts. However, optimizing all applications executed on VEs is a very time-consuming and cumbersome task for programmers. Therefore, we propose a method to automatically avoid memory access conflicts. First, we introduce a metric that can predict memory memory access conflicts based on memory addresses. Then, based on the metric, we implement an array-like C++ class that automatically avoids memory access conflicts. We evaluate the performance gain by our approach using a simple benchmark and kernel codes of a computational fluid dynamics application. The evaluation results demonstrate that the proposed method can successfully reduce the negative effects of memory access conflicts on performance.

Mapping MPI processes to processor cores, called process mapping, is crucial to achieving the scalable performance on multi-core processors. By analyzing the communication behavior among MPI processes, process mapping can improve the communication locality, and thus reduce the overall communication cost. However, on modern non-uniform memory access (NUMA) systems, the memory congestion problem could degrade performance more severely than the locality problem because heavy congestion on shared caches and memory controllers could cause long latencies. Most of the existing work focus only on improving the locality or rely on offline profiling to analyze the communication behavior. We propose a process mapping method that dynamically performs the process mapping for adapting to communication behaviors while coordinating the locality and memory congestion. Our method works online during the execution of an MPI application. It does not require modifications to the application, previous knowledge of the communication behavior, or changes to the hardware and operating system. Experimental results show that our method can achieve performance and energy efficiency close to the best static mapping method with low overhead to the application execution. In experiments with the NAS parallel benchmarks on a NUMA system, the performance and total energy improvements are up to 34% (18.5% on average) and 28.9% (13.6% on average), respectively. In experiments with two GROMACS applications on a larger NUMA system, the average improvements in performance and total energy consumption are 21.6% and 12.6%, respectively.

In this paper, we present results of the second phase of the project ExaFSA within the priority program SPP1648—Software for Exascale Computing. Our task was to establish a simulation environment consisting of specialized highly efficient and scalable solvers for the involved physical aspects with a particular focus on the computationally challenging simulation of turbulent flow and propagation of the induced acoustic perturbations. These solvers are then coupled in a modular, robust, numerically efficient and fully parallel way, via the open source coupling library preCICE. Whereas we made a first proof of concept for a three-field simulation (elastic structure, surrounding turbulent acoustic flow in the near-field, and pure acoustic wave propagation in the far-field) in the first phase, we removed several scalability limits in the second phase. In particular, we present new contributions to (a) the initialization of communication between processes of the involved independent solvers, (b) optimization of the parallelization of data mapping, (c) solver-specific white-box data mapping providing higher efficiency but less flexibility, (d) portability and scalability of the flow and acoustic solvers FASTEST and Ateles on vector architectures by means of code transformation, (e) physically correct information transfer between near-field acoustic flow and far-field acoustic propagation.

For large-scale efficiently parallelized electronic structure calculation within the GW approximation, we modified the MPI-parallelized version of the GW space-time program. To reduce the communication time required for computation of the inverse of the complex dielectric matrix, which is one of the bottlenecks of the program, the ScaLapack library codes employed for the LU-decomposition matrix inversion was replaced with the Lapack counterpart implemented with the intranode task parallelization. As a result, the elapsed time for matrix inversion significantly reduced, along with improvement on the parallelization efficiency for the number of nodes or cores. In addition, the intranode task parallelization for inversion with OpenMP was found to show reasonable parallelization efficiency with respect to the number of threads inside a node. Overall, the improvement in computation time will allow us to investigate not only the electronic structure of bulk phases, but also those of surfaces and interfaces of organic molecular crystals.

Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than SRAM and non-volatility, STT-RAM can contribute to building the cache memory with a larger capacity and a less static energy. However, since STT-RAM changes its magnetization state in the case when storing data, the energy cost of write access requests for an STT-RAM LLC is more expensive than that of an SRAM LLC. As a result, the total energy consumption of the STT-RAM LLC for write-intensive applications may increase. To solve this problem, this paper proposes an Adjacent-Line-Merging Writeback Scheme. Since a larger cache line of an STT-RAM cache can contribute to the reduction in the write energy cost per byte, the upper-level cache merges two adjacent small lines to one large line, and then writes the merged line back to the STT-RAM LLC. Moreover, the larger line size for the LLC leads to a reduction in the static energy cost. The evaluation results show that the proposed scheme can reduce the energy consumption of the STT-RAM LLC by up to 26, and 9.3 percent on average.

Achieving a high sustained simulation performance is the most important concern in the HPC community. To this end, many kinds of HPC system architectures have been proposed, and the diversity of the HPC systems grows rapidly. Under this circumstance, a vector-parallel supercomputer SX-ACE has been designed to achieve a high sustained performance of memory-intensive applications by providing a high memory bandwidth commensurate with its high computational capability. This paper examines the potential of the modern vector-parallel supercomputer through the performance evaluation of SX-ACE using practical engineering and scientific applications. To improve the sustained simulation performances of practical applications, SX-ACE adopts an advanced memory subsystem with several new architectural features. This paper discusses how these features, such as MSHR, a large on-chip memory, and novel vector processing mechanisms, are beneficial to achieve a high sustained performance for large-scale engineering and scientific simulations. Evaluation results clearly indicate that the high sustained memory performance per core enables the modern vector supercomputer to achieve outstanding performances that are unreachable by simply increasing the number of fine-grain scalar processor cores. This paper also discusses the performance of the HPCG benchmark to evaluate the potentials of supercomputers with balanced memory and computational performance against heterogeneous and cutting-edge scalar parallel systems.

Three-dimensional stacked integrated circuits (3D-SICs) have been expected to overcome the limitations of conventional two-dimensional (2-D) implemented circuits. Since a stacking strategy affects the performance and the power consumption of 3D-SICs, this paper examines two stacking strategies for designing the 3-D stacked floating-point fused multiplyadd (FP-FMA) module which contains four FP-FMA units. Experimental results show that a coarse-grain stacking strategy is suitable for reducing critical path delay of the 3-D stacked FP-FMA module. On the other hand, a fine-grain stacking strategy is suitable for reducing power consumption. The 3-D stacked FP-FMA module which is designed based on a fine-grain stacking strategy achieves an 8.4% critical path delay reduction and an 18% average power reduction compared with the 2-D implementation.

The emergence of various high-performance computing (HPC) systems compels users to write a code considering the characteristic of each HPC system. To describe the system-dependent information without drastic code modifications, the directive sets such as the OpenMP directive set and the OpenACC directive set are proofed to be useful. However, the code becomes complex to achieve high performance on various HPC systems because different directive sets are required for various HPC systems. Thus, the code-maintainability and readability are degraded. This paper proposes a directive generation approach that generates various kinds of directive sets using user-defined rules. Instead of using several kinds of directive sets, users only have to write special placeholders that are utilized to specify a unique code pattern where several directives are inserted. Then, the special placeholders trigger the generation of appropriate directives for each system using a user-defined rule with a code transformation framework Xevolver . Because only special placeholders are inserted in the code, the proposed approach can keep the code-maintainability and readability. From the performance evaluations of directive-based implementations on various HPC systems, it is shown that the best implementation is different among the HPC systems. Then, through the demonstration of transformation into multiple kinds of implementations, the proposed approach can successfully generate directives from a smaller number of special placeholders. Therefore, it is clarified that the proposed directive generation approach is effective to keep the maintainability of a code to be executed on various HPC systems.

This paper presents an OpenCL-like offload programming framework for NEC SX-Aurora TSUBASA (SXAurora). Unlike traditional vector systems, one node of an SXAurora system consists of a host processor and some vector processors on PCI-Express cards, which are called a vector host and vector engines, respectively. Since the standard OpenCL execution model does not naturally fit in the vector engine, this paper discusses how to adapt the OpenCL specification to SXAurora while considering the trade off between performance and code portability. Performance evaluation results clearly demonstrate that, with a moderate programming effort, the proposed framework can express the collaboration between a vector host and a vector engine so as to make a good use of both of the two different processors. By delegating the right task to the right processor, an OpenCL-like program can fully exploit the performance of SX-Aurora.

A modern memory system is equipped with many memory channels to obtain a high memory bandwidth. To take the advantage of this organization, applications’ data are distributed among the channels and transferred in an interleaved fashion. Although memory-intensive applications benefit from a high bandwidth by many memory channels, applications such as compute-intensive ones do not need the high bandwidth. To reduce the energy consumption for such applications, the memory system has low-power modes. During no memory request, the main memory can enter these modes and reduce energy consumption. However, these applications often cause intermittent memory requests to the channels that handle their data, resulting in not entering the low-power modes. Hence, the memory system cannot enter the low-power modes even though the applications do not need the high bandwidth. To solve this problem, this paper proposes a dynamic data allocation mechanism for many-channel memory systems. This mechanism forces data of such applications to use the specified channels by dynamically changing the address-mapping schemes and migrating the data. As a result, the other channels to which the data are not allocated can have a chance to enter the low-power modes for a long time. Therefore, the proposed mechanism has the potential to reduce the energy consumption of many-channel memory systems. The evaluation results show that this mechanism can reduce the energy consumption by up to 11.8% and 1.7% on average.

Peachy Parallel assignments are high-quality assign- ments for teaching parallel and distributed computing. They have been successfully used in class and are selected on the basis of their suitability for adoption and for being cool and inspirational for students. Here we present a fire fighting simulation, thread- to-core mapping on NUMA nodes, introductory cloud computing, interesting variations on prefix-sum, searching for a lost PIN, and Big Data analytics.

MPI process mapping is an important step to achieve scalable performance on non-uniform memory access (NUMA) systems. Conventional approaches have focused only on improving the locality of communication. However, related studies have shown that on modern NUMA systems, the memory congestion problem could cause more severe performance degradation than the locality problem because a high number of processor cores in the systems can cause heavy congestion on shared caches and memory controllers. To optimize the process mapping, it is necessary to determine the communication behavior of the MPI processes. Previous methods rely on offline profiling to analyze the communication behavior, which incurs a high overhead and is potentially time-consuming. In this paper, we propose a method that automatically performs MPI process mapping for adapting to communication behaviors while considering both locality and memory congestion. Our method works at runtime during the execution of an MPI application. It does not require modifications to the application, previous knowledge of the communication behavior, or changes to the hardware and operating system. The proposed method has been evaluated with the NAS parallel benchmarks on a NUMA system. Experimental results show that our method can achieve performance close to an oracle-based mapping method with low overhead to the application execution. The performance improvement is up to 27.4% (13.4% on average) compared with the default mapping of the MPI runtime system.

This paper focuses on the convolutional neural network (CNN) accelerator with a three-dimension stacking integrated circuit (3DSIC) technology. In order to implement a CNN accelerator into several layers by using 3DSIC technology, circuit designers should consider several problems such as how many floating-point units and register-files implement on one layer, and how to place these. Because of these problems will affect the performance of the 3-D stacked CNN accelerator. This paper proposes a design scheme of the module for a 3-D stacked convolutional neural network accelerator, which consists of several half-precision floating-point fused multiply-add units and weight register-files. The proposed scheme achieves up to a 10% power consumption reduction compared to a 2-D implemented module when the number of units and register-files is sixteen, and the number of layers is two.

This paper proposes a novel file transfer tool to improve file transfer performance over Japan high performance computing and networking (JHPCN). We first develop a high-performance and flexible protocol (HpFP) for inter-datacenter transport network. An original HpFP is designed first for specified networks and puts more emphasis on latency and packet loss tolerances than fairness and friendliness, while an enhanced HpFP is more suitable for real network environments. Then, based on the enhanced HpFP, we implement a file transfer tool, called high-performance copy (HCP). The performance of our file transfer tool is evaluated between datacenters of JHPCN using real datasets collected from supercomputer resources. The results show that the HCP achieves higher throughput than traditional tool for file transfer over JHPCN.

Thread mapping is crucial to improve the performance and energy consumption of modern NUMA systems. In this work, we investigate the impacts of locality and memory congestion-aware thread mapping on the energy consumption. Our evaluation shows that considering both the locality and memory congestion can significantly reduce not only the performance but also the total energy consumption, though it could potentially increase the interconnect traffic and also cache misses.

Modern supercomputers consist of multi-core processors, and these processors have recently employed vector instructions, or so-called SIMD instructions, to improve performances. Numerical simulations need to be vectorized in order to achieve higher performance on these processors. Various legacy numerical simulation codes that have been utilized for a long time often contain two versions of source codes: a non-vectorized version and a vectorized version that is optimized for old vector supercomputers. It is important to clarify which version is better for modern supercomputers in order to achieve higher performance. In this paper, we evaluate the performances of a legacy fluid dynamics simulation code called FASTEST on modern supercomputers in order to provide a guidepost for migrating such codes to modern supercomputers. The solver has a nonvectorized version and a vectorized version, and the latter uses the hyperplane ordering method for vectorization. For the evaluation, we also implement the red-black ordering method, which is another way to vectorize the solver. Then, we examine the performance on NEC SX-ACE, SXAurora TSUBASA, Intel Xeon Gold, and Xeon Phi. The results show that the shortest execution times are with the red-black ordering method on SX-ACE and SX-Aurora TSUBASA, and with the non-vectorized version on Xeon Gold and Xeon Phi. Therefore, achieving a higher performance on multiple modern supercomputers potentially requires maintenance of multiple code versions. We also show that the red-black ordering method is more promising to achieve high performance on modern supercomputers.

This paper presents an OpenCL-like offload programming framework for NEC SX-Aurora TSUBASA (SX-Aurora) and also discusses the benefit of employing metaprogramming to describe architecture-specific parts of the programs. Unlike traditional vector systems, one node of an SX-Aurora system consists of a host processor and some vector processors on PCI-Express cards, which are called a vector host and vector engines, respectively. Since the standard OpenCL execution model does not naturally fit in the vector engine, this paper discusses how to adapt the OpenCL specification to SX-Aurora while considering the trade off between performance and code portability. This paper employs OpenCL to minimize non-portable parts of an application code for offload programming, and then metaprogramming to describe the non-portable parts. Performance evaluation results clearly demonstrate that, with a moderate programming effort, the proposed framework can express the collaboration between a vector host and a vector engine so as to make a good use of both of the two different processors. By delegating the right task to the right processor, an OpenCL-like program can fully exploit the performance of SX-Aurora. Moreover, metaprogramming can express vectorization-aware performance optimization to enhance the performance portability across different architectures including SX-Aurora.

As the diversity of high-performance computing (HPC) systems increases, even legacy HPC applications often need to use accelerators for higher performance. To migrate large-scale legacy HPC applications to modern HPC systems equipped with accelerators, a promising way is to use OpenACC because its directive-based approach can prevent drastic code modifications. This paper shows translation of a large-scale simulation code for an OpenACC platform by keeping the maintainability of the original code. Although OpenACC enables an application to use accelerators by adding a small number of directives, it requires modifying the original code to achieve a high performance in most cases, which tends to degrade the code maintainability and performance portability. To avoid such code modifications, this paper adopts a code translation framework, Xevolver. Instead of directly modifying a code, a pair of a custom code translation rule and a custom directive is defined, and is applied to the original code using the Xevolver framework. This paper first shows that simply inserting OpenACC directives does not lead to high performance and non-trivial code modifications are required in practice. In addition, the code modifications sometimes decrease the performance when migrating a code to other platforms, which leads to low performance portability. Â The direct code modifications can be avoided by using pairs of an externally-defined translation rule and a custom directive to keep the original code unchanged as much as possible. Finally, the performance evaluation shows that the performance portability can be improved by selectively applying translation with the Xevolver framework compared with directly modifying a code.

Since recent scientific and engineering simulations require heavy computations with large volumes of data, High-performance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is increasing, however, the performance of the memory system is constrained. The bytes per flop (B/F), which is a ratio of the memory bandwidth to the flop/s, for the HPC systems have been reduced with the evolution of the HPC systems. To fully exploit the potential of the recent HPC systems, and to meet the increasing demand for large memory, it is necessary to optimize practical scientific and engineering applications, considering not only the parallelism of the applications, but also the limitations of the memory subsystems of the HPC systems. In this paper, we discuss a set of approaches to optimization of the memory access behavior of the applications, which enable their executions with improved performance on the recent HPC systems. Our approaches include memory optimizations through memory footprint controlling, restructuring of data structures for active elements, redundant data structure elimination through combined calculations and optimized re-calculation of data. To validate the effectiveness of our approaches, a plasmonics simulation application is evaluated on vector platforms NEC SX-ACE, NEC SX-9, and Intel Xeon based platform NEC LX 406-Re2. By applying our approaches to the implementation, the memory usage of the plasmonics simulation application can be reduced up to nearly 1/71 of the original, and its execution can be possible on a single node of a distributed parallel system with smaller memory capacity. The optimization results in 1.14 times faster execution on SX-ACE and 1.81 times faster execution on LX 406-Re2.

Since different systems usually require different performance optimizations, an application code is likely “specialized” for a particular system configuration to fully extract the system performance. This is one major reason why migration of an existing application code, so-called legacy code migration, is so labor-intensive and error-prone especially in the high-performance computing (HPC) area. To make matters worse, the diversity of system architectures would increase the number of system configurations that have to be considered during the life of an application. As a result, the increasing system complexity and diversity will force programmers to further invest enormous time and effort on HPC application development and maintenance. For long-term software development and maintenance, an HPC application code should not be optimized for a particular system configuration. However, simply excluding system-awareness from the code just results in reducing the performance, because system-awareness can be regarded as the necessary information to exploit the performance of the target system. The goal of this project is to express system-awareness separately from the HPC application code to achieve high performance while keeping the code maintainability. To this end, we have been developing a code transformation framework, Xevolver, so that users can express system-awareness as user-defined code transformation rules separately from HPC application codes. By defining custom code transformations for individual cases, an HPC application code itself does not need to be modified for each system configuration and is transformed for each system by using the code transformations defined separately from the code.

Most machine learning models use hyperparameters empirically defined in advance of their training processes in a time-consuming and try-and-error fashion. Hence, there is a strong demand for systematically finding an appropriate hyperparameter configuration in a practical time. Recent works have been interested in Bayesian Optimization to tune the hyperparameters with a less number of trials, using a Gaussian Process to determine the next hyperparameter configuration being sampled for evaluation. Most of the works use some criteria including the probability of improving (GP-PI), the expected improvement (GP-EI), and the upper confidence bounds (GP-UCB), without consideration of the execution time of each trial. In this paper, we focus on minimizing the total execution time to find an appropriate configuration. Specifically, we propose to take the execution time of each trial into account. We demonstrate the feasibility of the proposed approach and show that our proposal can find an optimal or suboptimal hyperparameter configuration faster than other Bayesian optimization-based approaches in terms of execution time.

Checkpointing with a constant checkpoint interval, a so-called constant checkpointing method, is commonly used in HPC field and has been proved to be the optimal solution for failures whose inter-arrival times are distributed exponentially. On the other hand, previous works have shown that there is a high correlation between processor temperature and its failure rate. By analyzing the results of the temperature monitoring on a parallel application, we noticed that the failure rate is dynamically changing and the failure inter-arrival times do not follow an exponential distribution. Under such a scenario, the constant checkpointing method is not the optimal solution and thus a checkpointing method with an adaptive checkpoint interval, called an adaptive checkpointing method, is required to achieve high performance. However, to use the adaptive method, the processor temperature must be constantly monitored in order to decide the timing for checkpointing. In this paper, we propose an adaptive checkpointing method with less reliance on the temperature monitoring. Our proposed method uses the timings of already occurred failures, called the prior failures, to estimate the mean time to failure (MTTF) of the next failure, called the posterior failure. The timing of the posterior failure is predicted based on the characteristic of a truncated Weibull distribution. The simulation results show that the proposed method can reduce the total wasted time compared to the constant checkpointing method with a considerably small temperature monitoring period.

It is hard to envision all possible use cases or environmental conditions that might happen to a VLSI system during its lifetime and could adversely affect its performance and/or dependability. The job of designing and testing a VLSI includes the challenge of being prepared even against problems hard to foresee, within the restrictions of practical cost and time. This chapter is intended to offer a perspective for unidentified future threats to dependability and provisions in design and test that could be taken to mitigate them. First of all, in Sect. 12.1, we look back on the trend in the fault causes experienced over time, and discuss unidentified future threats and technical challenges. Section 12.2 takes up the cloud data center that provides IaaS (Infrastructure as a Service) as a typical electronic system requiring high levels of dependability from a few different subsystem perspectives, i.e., server, storage, and communications, and discusses relevant emerging requirements. In Sect. 12.3, the concept of “patchable hardware and rectification for post-Silicon validation” is introduced. Section 12.4 deals with collecting the field test data for preventive maintenance and potentially for post-failure analysis and future study based on the technology called DART (Dependable Architecture with Reliable Testing). Section 12.5 deals with the fault detection and reconfiguration method for multiple-core processor is discussed. Finally, in 12.6, checkpoint-restart for heterogeneous multiple processor systems is proposed as a standard procedure for dependability.

Since it is difficult to explicitly express the underlying relationship between a code and appropriate optimizations for it, this paper discusses a possibility of using machine learning to predict appropriate optimizations for a given code. In this paper, selection of appropriate compiler options is taken as an example of the prediction, because it can be seen as selection of code optimizations; use of different compiler options results in enabling different compiler optimizations. One severe problem is that it is difficult to collect a sufficient number of data for a machine learning model to well understand the underlying relationships among codes and their appropriate optimizations. Therefore, in addition to conventional features of a code, such as profiling data and parameterized code features, we directly use a code structure itself to retrieve more information from a limited number of codes. The evaluation results suggest that use of code structural features can potentially improve the prediction accuracy if the training dataset contains data of similar code structures.

Since embedded DRAM (eDRAM) has a higher density with a lower leakage power than SRAM, it is promising to be used as the last-level cache (LLC) of a microprocessor. However, an eDRAM LLC needs a high energy consumption for refresh operations. In particular, the conventional eDRAM LLC refreshes even dead cache lines that are not reused until their evictions. This paper proposes an energy-aware set-level refreshing mechanism to reduce the wasted energy due to unnecessary refreshes of dead cache lines. In the case where the cache resources are excessive compared with the demand of an application, the excessive resources are wasted to store dead lines. Therefore, the proposed mechanism dynamically adjusts the number of refreshed cache lines. The evaluation results show that the proposed mechanism can reduce the LLC energy consumption by 46% with a 1% performance loss on average.

MPI process placement is an important step to achieve scalable performance on modern non-uniform memory access (NUMA) systems. A recent study on NUMA architectures has shown that, on modern NUMA systems, the memory congestion problem could cause more severe performance degradation than the data locality problem because heavy congestion on memory controllers could cause long latencies. However, conventional work on MPI process placement has focused on locality to minimize the remote-access communication. Moreover, maximizing the locality may actually degrade performance because the load imbalance among nodes in a modern NUMA system may increase. Thus, a process placement algorithm must be designed to consider memory congestion. In this paper, a method to reconcile both the locality and the memory congestion on modern NUMA systems is proposed. This method statically analyzes the application communication pattern to optimize the process placement. A data clustering method is applied to the time-series data of the MPI communications in order to identify data traffics that potentially cause memory congestion. The proposed method has been evaluated with the NPB kernels on a real NUMA system and a simulation environment. Experimental results show that the proposed method can achieve 1.6x performance improvement compared with the current state-of-the-art strategy.

The rapid evolution of HPC systems brings us a high computational capability. However, it is getting harder to exploit the potential of an HPC system due to the increases in system complexity. This fact forces computational scientists to create complicated programming, which causes low productivity and maintainability. To overcome this situation, we are aggregating various optimization patterns and building a knowhow database of system-aware code optimizations called an HPC refactoring catalog. This paper discusses the design and implementation of an HPC refactoring catalog and shows a case study to demonstrate the practicality of the catalog.

Although incremental checkpointing is an effective way of reducing the checkpointing overhead, it has been discussed mostly for system-level checkpointing. Since the whole memory space of a running application is saved in a checkpoint file, system-level checkpointing will be less practical for future-generation extreme-scale computing systems, in which the I/O operation is much more expensive than the computation, especially in terms of power consumption. In this work, hence, the idea of incremental checkpointing is applied to application-level checkpointing, in which programmers explicitly specify the simulation data to be saved into a checkpoint file so that only necessary data for resuming the simulation are saved. This work assumes that, in incremental checkpointing, a management region consisting of multiple memory pages is written to a checkpoint file only if any page in the management region has been updated since the last checkpointing. A management granularity is defined as the number of pages in a management region. A large granularity is likely to reduce the checkpointing overhead if a management region consists of only updated pages. However, if the granularity is too large, a management region will contain a lot of pages not updated since the last checkpointing, and thus incremental checkpointing cannot reduce the number of pages to be written into a checkpoint file. Therefore, this paper proposes an application-level incremental checkpointing mechanism with granularity autotuning for reducing the checkpointing overhead of a legacy simulation code.

As the SIMD width of modern microprocessors has been widening for keeping up with the computational demand for HPC systems, recently the vector architecture comes back to spotlight. Besides, a modern vector architecture that has been keeping a large SIMD width and a high B/F ratio has survived and evolved in the HPC community. In this paper, to clarify the potential of the modern vector architecture, we present the performance and power analysis of a modern vector supercomputer SX-ACE using HP-X benchmark programs (HPL, HPCG, and HPGMG). Furthermore, the implementation and optimization of these benchmarks on SX-ACE are discussed. The evaluation results show that SX-ACE achieves the highest efficiencies in the HPGMG and HPCG ranking lists. These facts clearly indicate that the powerful vector processing mechanism with a high B/F ratio is mandatory to achieve a high sustained performance in the future HPC systems.

The cost of maintaining an application code would significantly increase if the application code is branched into multiple versions, each of which is optimized for a different architecture. In this work, default and vector versions of a realworld application code are refactored to be a single version, and the differences between the versions are expressed as userdefined code transformations. As a result, application developers can maintain only the single version, and transform it to its vector version just before the compilation. Although code optimizations for a vector processor are sometimes different from those for other processors, application developers can enjoy the performance of the vector processor without increasing the code complexity. Evaluation results demonstrate that vectorizationaware loop optimization for a vector processor can be expressed as user-defined code transformation rules, and thereby significantly improve the performance of a vector processor without major code modifications.

Modern memory systems are equipped with multiple channels to achieve a higher memory bandwidth. Since the multi-channel memory system focuses on achieving a high memory bandwidth, data are allocated to all the channels. Hence, when the memory system is accessed, all the channels are activated until the next DRAM refresh starts. Therefore, when executing compute-intensive applications that do not need a full memory bandwidth, the memory modules just waste power because of an unnecessary activation. To overcome this problem, this paper proposes a data allocation method, which controls the number of accessed channels for reducing energy consumption according to applications' demands for the memory bandwidth. The evaluation results show that the proposed method reduces the energy consumption by up to 10.4%, and 5.3% on average without degrading the performances.

Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.

The appearance of various high-performance computing (HPC) systems compels a user to write a code considering the characteristic of each HPC system. To describe the system-dependent information without drastic code modifications, the directive sets such as the OpenMP directive set and the OpenACC directive set are useful. However, a code becomes complex to achieve high performance on various HPC systems because different directive sets are required for each HPC system. Thus, the code maintainability and readability are degraded. This paper proposes a directive generation approach that generates various kinds of directive sets using user-defined rules. Instead of several kinds of directive sets, a user writes a special placeholder that is utilized to specify a unique code pattern where several directives are inserted. Then, the special placeholder triggers generation of appropriate directives for each system using a user-defined rule with a code translation framework Xevolver. Because only special placeholders are inserted in a code, the proposed approach can keep the code maintainability and readability. From the demonstration of translation into three kinds of directive-based implementations, it is clarified that the proposed approach can replace directives into a smaller number of special placeholders. Moreover, it is clarified that the proposed approach can realize high performance portability by generating appropriate directives for each HPC system.

The last-level cache (LLC) of a modern chip-multiprocessor (CMP) keeps two kinds of data: shared data accessed by multiple cores and private data accessed by only one core. Although the former are likely to have a larger performance impact than the latter, the LLC manages both of those data in the same fashion. To realize a highly efficient execution on a CMP, this paper proposes a cache partitioning mechanism to protect shared data from excessive eviction. The evaluation results show that the proposed mechanism improves the performance by up to 76% and by 8% on average at a cost of less than 2% of the LLC hardware.

This paper proposes a directive translation approach that translates a special placeholder to different directives, depending on the target HPC system. The special placeholder in an application code is used as a trigger for the directive translation. By employing a code translation framework, Xevolver, the special placeholder can be translated to various directives that fit to any target HPC systems. Instead of using multiple directives, it can keep maintainability and readability of the original code because only special placeholders are inserted into an application code. This paper also demonstrates a translation of a special placeholder into OpenMP directives to clarify the effectiveness of the proposed directive translation approach.