Search

The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

Recent advances in the field of AI have proved that deep neural networks perform and recognize arrhythmia better than cardiologists when trained with a large chunk of data. However, despite the better performance, deep neural networks demand more resources. Therefore, in this paper, a new deep neural network using low resources has been proposed while maintaining high performance, and it is enhanced with a depthwise separable convolution layer for Electrocardiogram (ECG) classification. The algorithm is performed on the Physikalisch-Technische Bundesanstalt (PTB) diagnostic dataset taken from Physionet consisting of two classes: Myocardial Infarction (MI) and Normal (N). Our simulation results show that the proposed lightweight DNN provides high performance with almost the same accuracy as conventional SquezeNets.

Multi-threshold null convention logic (MTNCL) is a novel low power paradigm for designing asynchronous null convention logic (NCL) circuits. To further reduce the dynamic power consumption, a new methodology that utilizes gate diffusion input technique is proposed. The proposed approach is used to realize MTNCL gates and a decrease in the transistor count is observed that tend to reduce the dynamic power consumption. Compared to SMTNCL approach, the proposed methodology shows a 5.6% is reduction in the power consumption for the MTNCL gates.

A single-inductor dual output boost converter behavioral model was designed using a 180nm CMOS technology and VerilogA. The converter adopts time-multiplexing control by providing independent supply voltages (3.0V and 4.0V) and adjustable peak current for dual output system loads including battery charging. The converter was analyzed and compared to existing architectures presented in literature in the aspects of power path and control scheme. The proposed topology and control loop can be extended to include additional outputs. Implementation of the power stage, controller, and functional blocks are discussed.

In this work, the modeling of spiking neurons and their VLSI implement issues are evaluated and discussed in detail in terms of silicon area, power, and stability considering nanometer technologies process, voltage, and temperature variations. Considering low power requirement and stability, Hindmarsh-Rose model turns out to be the best choice for neural network implementation because of its affordable cost and rich neural features. Although other models such as Leaky Integrate-and-Fire model costs less, it is limited by its poor neural plausibility.

Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

Null convention logic is a commonly used delay insensitive paradigm for designing asynchronous circuits. Traditionally, NCL circuits are implemented using static complementary metal oxide semiconductor (CMOS) technology that tends to have large area overhead. To address this issue, a gate diffusion input (GDI) methodology is introduced for realizing NCL circuits. This GDI is a low-power design approach that uses only two transistors to design complex circuits. By using this design technique, a significant reduction area utilization was observed at the expense of latency overhead. To address this limitation, a novel design approach based on GDI methodology is proposed in this paper. The proposed fast GDI (FGDI) approach uses GDI functions F1 and F2 to reduce latency without affecting performance. To evaluate the performance of the FGDI technique, a one-bit full adder was realized in Cadence virtuoso 45nm technology. Compared to GDI implementation, FGDI approach shows a 76% reduction in the latency.

Graphical Processing Units (GPUs) are always criticized for high power consumption due to its massive performance that it can deliver. While GPUs are getting into the mobile market, more power constraints are established. In this work, we evaluate the power gating techniques for GPU cache arrays. The leakage power in active mode is measured at 2.28 µW whereas is sleep mode leakage power is measured at 0.61 µW (26.7% of active mode leakage) and 0.034 µW at off mode (1.5% of active mode leakage) at 1.0V power supply using 45nm standard CMOS process.

Cardiovascular diseases (CVDs) are the number one cause of death today. Therefore, the early detection of arrhythmia is very important for cardiac patients. This paper proposes the heartbeat classification algorithm using the electrocardiogram(ECG) signals. An ECG is a 1D signal that is the result of recording the electrical activity of the heart using an electrode. In this paper, a single-layer Tensorflow LSTM model has been proposed to classify a biological time-series consisting of normal and abnormal heartbeats. The method was evaluated using the publicly available Physio net's MIT-BIH Arrhythmia dataset. The dataset has been divided into training and testing data. As a result, the classifier achieved a 95% average accuracy. Compared with the other CNN and RNN models used for the heartbeat classification, the simulation result shows the proposed algorithm has higher accuracy.

Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based computations, however, are not only susceptible to noise and other skin color segments but also inherently sequential and difficult to efficiently parallelize. In this paper, we implement and accelerate our in-house distance image based approach using CPU-GPU heterogeneous computing. Using emerging CPU-GPU heterogeneous computing technology, we achieved 5.0 times speed-up for 320x240 images, and 17.5 times for 640x480 images and our experiment demonstrates that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate, 80.4% of which have more than 3 fingers detected on commodity processors.

The increasing power consumption in the synchronous circuits is the major concern in the semiconductor industry. The major contributor to this power consumption is the clock generator and the clock distribution. This problem can be addressed by using the asynchronous circuits. Null Convention Logic (NCL) is one of the most commonly known delay insensitive approach for designing asynchronous designs. However, realizing the NCL circuits using the commonly used complementary metal oxide semiconductor (CMOS) technique is said to increase the area and the power consumption. The low power design technique known as Gate Diffusion Input (GDI) can be used for implementing the NCL circuits to reduce both the area and the power. Application of the external input to the sources of the pMOS and nMOS transistors, allows to reduces the area and the dynamic switching. Thus, decreasing the transistor count and the power. The proposed GDI NCL technique is used for designing the 4-bit un-pipelined NCL multiplier. The design was realized and simulated in gpdk045 Cadence Virtuoso. In comparison to the CMOS model, the GDI model shows 21.6 % in transistor count and the dynamic power is reduced by 13.7 %.

Stochastic computing as a computing paradigm is currently undergoing revival as the advancements in tech-nology make it applicable especially in the wake of the need for efficient reduced precision computing for emerging applications. Recent research in stochastic computing exploits the benefits of approximate computing, called Approximate Stochastic Computing (ASC), which further reduces the op-erational overhead in implementing stochastic circuits. A new generalized adaptive method improving on ASC is proposed in this work. The proposed method has been discussed with two possible implementation variants - Area efficient and Time efficient. The proposed method has also been implemented in Matlab to compare against ASC and is shown to perform better than previous approaches for error-tolerant applications.

Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide semiconductor (CMOS) technology is usually used for implementing the NCL circuits, which as a major drawback of large area consumption and power dissipation. These limitations have been addressed by adopting a low-power design technique called Gate Diffusion Input (GDI) in this work. GDI technique allows implementing primitive logic gates using only two transistors. Thus, it not only reduces the transistor count but also the power consumption. However, GDI technique suffers a significant voltage drop across the circuit, due to its inherent voltage swings. Thus, to ensure full swing output regenerative buffers are added at the output stage which tends to increase the overall latency. In this work, a novel GDI and HYBRID (CMOS+GDI) designs are proposed to overcome the limitations of the CMOS-NCL designs. The proposed approaches were tested by realizing NCL Ripple Carry Adder (RCA). The proposed model was simulated in Cadence Virtuoso and power reduction of 14.9 % and 9.8 % has been observedfor GDI and HYBRID models, respectively.

Lately, stochastic computing (SC) has been found to be significantly advantageous in image processing applications because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to excessive run-time requirement. In this paper, a new technique called the variable bit truncation approximate stochastic computing (ASC) approach focusing on image processing applications is proposed to reduce the computation time of a SC with an acceptable trade-off in accuracy. The proposed technique is to variably truncate the low-order bits of the image pixel value depending on the application and the accuracy limits. Experimental results on standard test images for multiple image processing applications suggest that by using this approach acceptable output images can be generated using stochastic computation at a much faster way.

The clothing materials are ubiquitous part of our everyday life for thousands of years. However, despite this they have largely not been considered as an input surface in human device interactions, but that is until more recently as today's developments of wearable sensors, that are small and flexible in nature, have open this platform. The clothing materials' shape-changing nature enables the users to perform gestures (e.g., bend or stretch) not possible when compared to the interaction methods of flat touchscreens of mobile devices. In addition, the clothing-based interfaces by default have the unique advantage of being placed anywhere on the body and always being with the wearers and their devices. In this paper, we validate the use of clothing-based wearable sensors to support interacting with mobile devices and present some challenges to be overcome for clothing-based interfaces to be adopted more widely.

Nowadays, robots take more charges of human activities, especially in repeated tasks, daily homecare and emergency rescue. Instead of using a solo robot to execute specific tasks, it calls for multi robots to cooperate in more scenarios, especially doing complex and difficult tasks that a single robot could not complete. In this paper, firstly it demonstrates a simplified model of the real disaster rescue scenario where requires robots to remove rocks from the road. Then it discusses the system how multi robots communicate wirelessly and cooperate together based on this abstract scenario. Finally, it evaluates and reflects the built system.

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn`t require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency.

SC (stochastic computation) has been found to be very advantageous in image processing applications because of its lower area consumption and low-power operation. However, one of the major issues with the SC is its long run-time requirement for accurate results. In this paper, a new technique called the approximate stochastic computing (ASC) approach called the approximate stochastic computing (ASC) focusing on image processing applications is proposed to reduce the computation time of a SC by a factor of 16 at a trade-off of an error percentage of 3.13% in the absolute stochastic value ([0,1)) computed. The proposed technique considers only the first four MSBs of the image pixel value for SC, which introduce a maximum error of 6.25% in the stochastic output. Attempts have been made to reduce this error to 3.13% by linearly increasing the clock cycles from 16 to 17 rather than exponentially (ex: 32, 64,128,256…). Experimental results from SC edge detection circuit indicate that this technique is a promising approach for efficient approximate image processing.

Any real architecture designed only in the CNFET technology as a hopeful substitution of the silicon CMOSFET has not been developed because of shortage of self-assembly CNFET technology for designing complex CNFET structures. Therefore, for designing the real architecture in the current self-assembly CNFET technology, the development of a simple CNFET circuit structure forming all the digital function is required. This paper proposes a simple CNFET circuit structure using back-gate voltages to design the real digital architecture and to overcome the high fabrication cost of CNFETs and manufacturing variability and imperfection of CNFET technology. The function of the proposed CNFET cell is determined by the back-gate voltages, and the determined function is the same as NAND or NOR gate function. The simulation results present that the propagation delay time of the ISCAS85 circuits in a 32nm Stanford CNFET technology deploying the proposed CNFET cells is reduced by over 42% compared to the conventional CNFET cell in ultra-low voltage (0.4V).

—In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency “dynamically”. The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated “automatically”. During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS’85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method. Keywords —PVT Variation sensors, Yield, Voltage Scaling, Frequency Scaling

This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The primary goal is the generation of a signal containing a known amount of each jitter component. This signal can then be used for testing high speed serial data channels. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining them are modeled, simulated and evaluated. Model simulation using Matlab is utilized to show the unique features of the components when they are combined into different injection sequences for producing the total jitter. Sequence dependency is investigated in depth and the validity of superposition of jitter components for typical values is confirmed. A good agreement between theory and simulation is verified; these results allow test engineers to have an insight into the interactions among jitter components in serial data channels.

This paper presents a feasibility study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electronic neurons based on Hindmarsh-Rose neuron dynamics and first order chemical synapses is modeled. The controller is based on a standard [email protected] CMOS process with 2V supply voltage. In order to achieve low power consumption, CMOS subthreshold circuit techniques are used. The controller generates an excellent replica of the walking motor program and allows switching between walking in different directions in response to different command inputs. The simulated power consumption is 4.8mW and die size including I/O pads is 2.2mm by 2.2mm. Simulation results demonstrate that the proposed design can generate adaptive walking motor programs to control the legs of autonomous robots.

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

This paper presents a novel modeling and analysis of inter-symbol interference (ISI)jitter in serial data channels either between chips or on chip. The simulation results show that ISI jitter is dependent on pole location, settling time, and damping ratio of the data serial channel. Based on the proposed ISI jitter model, the effect of the ISI jitter on other jitter components is illustrated along with realistic simulation results.

GPU (Graphics Processing Unit) is emerging as a key 3D/2D graphics and parallel workload accelerator in various SoC applications. As semiconductor fabrication technology continues to scale, chips (especially those with extremely high transistor counts such as processors) are becoming increasingly vulnerable to faults that could produce unwanted errors in computing. The most severe problem is Silent Data Corruption (SDC) because this fault insidiously generates erroneous outputs without being detected. This paper discusses the characterization of SDC vulnerability of GPU on various GPGPU (General Purpose computing on GPU) workloads.

3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias) is expected to overcome limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability in temperature (i.e., hotspots) is anticipated to result in bit error variation in DRAM die. A novel multi-stage BCH decoder has been proposed to efficiently address this issue in this work. The proposed multi-stage BCH decoder is designed to tolerate upto a certain maximum number of error bits per codeword, which is estimated from the on-line thermal gradient data, to minimize the decoding latency.

Hand detection plays an important role in Human Computer Interaction (HCI). Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based approaches, however, are easily distorted by noises and other skin color segments. In this paper, we present a distance image based approach using CPU-GPU heterogeneous computing. Our experiments demonstrate that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate where 80.36% of cases have more than 3 fingers detected on commodity processors. We also achieved 5.0 times speed-up for 320×240 images, and 17.5 times for 640×480 images.

This paper presents low power and low jitter phase locked loop (PLL) design using supply regulation and active loop filter (ALF) on 110nm CMOS technology and with 1V supply voltage. The supply voltage is regulated by low-dropout (LDO) regulator. The ALF filters high frequency noise of the VCO control voltage. The LDO regulator provides 0.8V output, −83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. The jitter of the PLL without and with LDO regulator is 44.9ps and 4.6ps, respectively.