Search

This work is about designing of thermal aware low power Vedic multiplier using Stub-Series Terminated Logic (SSTL). The design of Vedic multiplier is a part of Vedic arithmetic circuits design project. “Urdhva-Tiryagbhyam” sutra is used to design the Vedic multiplier. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. When we use SSTL135_R in place of SSTL12, SSTL12_DCI, SSTL15, and SSTL135_DCI, there is 42.5%, 82.7%, 28.12%, and 72.9% reduction in I/O power at 21 0 C, 40 0 C, 53.5 0 C and 56.7 0 C. This design is implemented on Artix-7 FPGA using Verilog as hardware description language and Xilinx ISE 14.1 as simulator.

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as "Paravart- yaYojayet". ParavartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cum- bersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have de- signed a Vedic divider to solve long divisions in seconds. Our design con- sists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathe- matics to solve DSP operations using Urdhava-Triyagbhayam multiplica- tion sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capac- itance maximum power is consumed at 100pF and minimum power is con- sumed at 20pF.

Stub-Series Terminated Logic (SSTL) IO standards and theory of Vedic Mathematics are used in design of Vedic multiplier. This vedic multiplier is a part of Vedic arithmetic circuits design project for Vedic Processor Design. This Vedic multiplier design is based on the formula “Urdhva-Tiryagbhyam” means Vertical and cross wise. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. There is 8.27% reduction in Total power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 14.19% reduction in IO power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 50% reduction in Total power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. There is 85.16% reduction in IO power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. This design is implemented on 28nm FPGA using Verilog and Xilinx Integrated System Environment 14.1. There is no change in Leakage power with change in IO standards. Leakage power depends on ambient temperature. In the other words, leakage power is directly proportional to ambient temperature. Keywords–SSTL, Low Power, Vedic Multiplier, IO Standard, FPGA

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

Multiplier is used for multiplication of a signal and a constant in Digital Signal Processing (DSP). 28nm tech-nology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and Xpower Analyser. Vedic multiplier gains speed improvements by parallelizing the generation of partial prod-ucts with their concurrent summations. In this work, we are exploring the feasibility of Vedic multiplier in Data Encryption Algorithm, DSP, reliable system, multimedia and fault tolerant systems. In our work, we are using 11 different IO standards from HSTL (High Speed Transistor Logic) and LVCMOS (Low Voltage Comple-mentary Metal Oxide Semiconductor) family. IO standards are used to match the impedance of transmission line, input/output port and device. The energy-efficient multipliers play a significant role in portable computing and communication systems also. Here we are using Field Programmable Gate Array (FPGA) in order to re-duce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy efficient Vedic multiplier. There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively.

In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind? This paper deals with that question and the whole work is going in direction to get solution of this problem with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard. LVCMOS is an acronym for low voltage complementary metal oxide semiconductor. In this Vedic multiplier, we are using three LVCMOS I/O standard. LVCMOS12 is available only in 65nm and 40nm FPGA. Rest LVCMOS18 and LVCMOS25 is available among 40nm, 65nm and 90nm FPGA. In order to test the thermal sustainability of our Vedic multiplier, we are testing it in three different room temperature 20°C, 30°C, and 40°C. Using LVCMOS25, there is 12.99%, 19.23% and 10.28% reduction in power dissipation on 90nm, 65nm and 40nm respectively. For LVCMOS25, when our Vedic multiplier design is migrated from 40nm design to 90nm design, there is 87.72% reduction in power dissipation of Vedic multiplier when temperature is constant 20°C.

Low Voltage Digitally Controlled Impedance (LVDCI) is an I/O standard available on FPGA. This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA. Selection of IO standard play an important role in power dissipation of design. Therefore, we are going to select the most energy efficient IO standards in LVDCI family for Vedic Multiplier. This Vedic multiplier design is a part of project of Vedic arithmetic circuits. The final deliverable of this project is Vedic Processor by merging both concepts of Veda, first book of this world, and the latest technology of this world. In order to test thermal aware design, we want to see that how does an electronic device behave if we change the temperature of surrounding in which it is working. For that purpose we have taken temperatures of four different regions. Furnace Creek Ranch is area of North America recorded the highest temperature of the world that is 56.7°C [1]. Approximately, 53.5°C is the maximum temperature recorded in Mohenjo-Daro situated in Sindh Pakistan [1]. We have also taken median temperature of Delhi i.e. 40°C and standard normal temperature i.e. 21°C. We are operating Vedic Multiplier with the four different temperature and different LVDCI IO standard and observe device performance, and power dissipation. When we use 28nm FPGA under room temperature of 40°C, there are 93.42%, 92.6%, 93.99%, 93.59% and 89.79% reduction in total power dissipation of Vedic multiplier using LVDCI 15, LVDCI 18, LVDCI DV2 15, LVDCI DV2 18 and HSLVDCI 15 respectively. Similarly, when we use 28nm FPGA, there is approximately 90-96% reduction in leakage power dissipation of Vedic multiplier using different LVDCI and different temperature. There is no change in I/O power with change in temperature for uniform IO standard. When we use different IO standard of LVDCI family, there is significant reduction in leakage power. FPGA based on 28 nm technology is more energy efficient than 40 nm technology based FPGA.