Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as "Paravart- yaYojayet". ParavartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cum- bersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have de- signed a Vedic divider to solve long divisions in seconds. Our design con- sists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathe- matics to solve DSP operations using Urdhava-Triyagbhayam multiplica- tion sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capac- itance maximum power is consumed at 100pF and minimum power is con- sumed at 20pF.