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A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100 K/s per channel.

This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35 mum CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100 MHz to 1.1 GHz.

The paper presents one kind of adiabatic driver for multi-port register file. Between decoder part and memory array, the adiabatic driver is added to reduce the power dissipation of word-line. At the same time, we also designed adiabatic sensing amplifier for register file. Adiabatic circuits require trapezoidal wave or sinusoidal wave as inputs and outputs. But the register file presented in this paper hasn't any requirement for inputs, so it can be easily used in embedded microprocessors. The experiment results show that the power dissipation of adiabatic register file reduces 40% versus traditional register file.

SRCMOS (self-resetting CMOS) is one kind of popular technique which can be used for designing high-speed circuits. This paper presents a new kind of locally self-resetting SRCMOS technique. According to the operational principle that the reset signal is generated by a mechanism local to its stage, the technique can realize high-speed circuits and has low design complexity. Based on the locally SRCMOS technique, the paper presents the design of a 32 word/spl times/64 bits 2write/6read eight-port register file. Using 1.8 V 0.18 /spl mu/m CMOS technology, simulation results show that the write access delay of the register file is 700 ps, and read access delay is 910 ps.

Microprocessors are extremely versatile and complexity that present significantly test challenges. This paper describes a retargetable functional test platform system design for various microprocessors. Characterized by configurable test environment generator, retargetable assembler and strong ATPG the platform system could automatically produce different test environment and assemble out relative test codes to adapt to the microprocessor under test. Experiments show that the platform system works correctly, flexibly and efficiently.

A design of a 32-bit microprocessor core PKURS002 for embedded system is presented in this paper. It consumes much less power yet remains the high performance, compared with its prior PKURS001. The core employs low power design techniques at the controller, data path and internal memorial cells. The controller employs distributed logic instead of centralized one to reduce the signal transition by enlarging the self-loop. A new algorithm LSA (Logarithmic Skip Adder) has been provided to implement ALU and bit-split technique is applied to the structure of register file. The core is described by HDL and verified on 0.35 mm CMOS process. Result shows it reduce 30% power consumption compared with its predecessor at the same performance.

In our project of IP library creation, MAC is an important IP module. Here, a new approach is proposed for designing high performance single cycle MAC. We combine the full custom design, gate level VHDL design and standard cell based synthesis together to get good performance and technology portability. After the technology is decided, basic circuit modules are custom designed and accurate HSPICE simulation is performed to generate exact driven, delay and area information. It is added to the standard cell library. We need to write the gate level HDL of a MAC using optimized special circuits, and then apply logic synthesis. Then the structure and the interconnection of MAC have been decided by the gate level netlist, it can get the good performance of full custom design and have better portability. When being changed to a new technology, the designer only need to redesign the small circuits and simulate them, the gate level netlist need no change. We compared the traditional 3-2 full adder, the redesigned 4-2 compressor, and the 9-2 compressor in this paper. The result is almost the same with the references. This new approach has advantages in IP reuse, shortens the developing times and can get the high performance of full custom design.

This paper gives a delay model of the register files which are made of multi-port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of register files, also there are some structure modifying for the storage cells of register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the register file is reduced by 11.5% than the register file which hasn't adopted novel method.

A multi-layer modeling approach is proposed in this paper for creating behavioral models of charge-pump phase-locked loops, which offers great flexibility of trading off between the simulation speed and accuracy. Also the approach allows time domain noise simulation with a specific layer. A multi-layer Verilog-A charge-pump PLL model is created to illustrate the proposed approach. A simulation speed up factor of 12 to 99 is achieved with reasonable loss of accuracy.

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.

A new Quadru-Tree algorithm, by which the transition probabilities of circuit nodes, including all internal and output nodes, can be exactly worked out, and its program implementation are presented in this paper. As evidence of its accuracy and efficiency, the result of one example run in the prototype is reported, as well.

An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.

With the rapid progress of information technology, security becomes one of the key factors in information storage, communication and processing. For the reason of speed and security, the requirement for VLSI chips or modules that support data encryption and decryption increases rapidly. The design and implementation of a data ciphering processor (DCP) chip adopting block cipher algorithm is demonstrated in this paper. The cipher algorithm is qualified for commercial use. The plaintext, ciphertext and key are all 64-bit long. A top-down design flow is used in the implementation. Several methods are employed to enhance the security of the chip. A standard-cell library is also developed in the design. All the design and implementation of this DCP are performed in China. A 0.9um double-layer-metal CMOS technology is adopted for manufacture. The chip achieves the required result in the first time implementation. The encryption/decryption processing speed reaches 40MBit/s.

We develop a novel algorithm for parameter extraction of semiconductor devices. The S/sup 3/ algorithm, which is functional for NP-hard problems in discrete space, is applied to the parameter extraction of BSIM (Berkeley Short-channel IGFET Model). By using this algorithm, a relatively large number of model parameters can be optimized globally and extracted simultaneously. As to BSIM1, two distinct S/sup 3/ smoothing strategies, accompanied by the LS-NR method, are used to extract the parameters. In contrast to the results obtained by using the LS-NR method alone, those derived after the introduction of these strategies are improved greatly.

Thispaperdescribesan8-bit125MHzlow-powerCMOSfully-foldinganalog-to-digitalconverter(ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 m CMOS technology and occupies a die area of 2 × 1.5 mm 2 . The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. In this paper, a novel mixed-averaging distributed T/H circuit is proposed which improves the accuracy and provides a better tradeoff between accuracy, size and power dissipation. In addition, a novel bit synchronization architecture is pre- sented to reduce the number of comparators, and this architec- ture employs folding circuits to produce a bit synchronization signal. Therefore, folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchroniza- tion block. A special low-power CMOS ADC is designed and only 22 comparators are used in the whole ADC. The ADC is implemented in 0.5 m CMOS technology. Measured results show that the power dissipation of the ADC is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

With analyzing features of the accumulator in numerically controlled oscillator (NCO), it is pointed out that design based on pipeline for NCO is feasible. The schematic and results of logic simulation are given in this paper. The pipeline based NCO has evidently more advantages: higher speed (about twice) and fewer components (about 2/3) than usual. >