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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

In conventional computing systems, the device imperfections constitute the main hindrance on the commercialization of emerging technologies. On the other hand, in alternative computing paradigms, generally acknowledged as unconventional computing, device imperfections can be utilized to achieve complex behaviors that are computationally hard for conventional computers. In Probabilistic Cellular Automata (PCA), complex collective phenomena emerge through simplistic locally coupled probabilistic entities, named as cells. However, the hardware implementations of PCA are highly imposed by the required randomness generation within each PCA cell. In this paper, a novel hardware design of 1-D PCA with Memristors is proposed, utilizing device’s non-volatile storage and its unprecedented voltage-controlled probabilistic switching behavior. The necessary theoretical framework for memristor-based PCA (MemPCA) is defined. Moreover, the randomness of MemPCA for various switching probability levels is evaluated through the entropy of generated sequences and the collective effect to all 1-D elementary CA rules is presented, highlighting the effectiveness of memristor as a source of entropy.

Risk analysis is an essential methodology for cybersecurity as it allows organizations to deal with cyber threats potentially affecting them, prioritize the defense of their assets, and decide what security controls should be implemented. Many risk analysis methods are present in cybersecurity models, compliance frameworks, and international standards. However, most of them employ risk matrices, which suffer shortcomings that may lead to suboptimal resource allocations. We propose a comprehensive framework for cybersecurity risk analysis, covering the presence of both intentional and nonintentional threats and the use of insurance as part of the security portfolio. A simplified case study illustrates the proposed framework, serving as template for more complex problems., Horizon 2020 Framework Programme. Grant Number: 740920 Ministerio de Economía y Competitividad. Grant Number: MTM2014‐56949‐C3‐1‐R AXA Research Fund. Grant Number: AXA‐ICMAT Chair on Adversarial Risk Analysis European Cooperation in Science and Technology. Grant Number: IS1304

Resistive Random Access Memory (ReRAM) is apromising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commercialization, mainly owing to the fact that the high fabrication variations and the stochastic switching of the manufactured ReRAM devices cause high Bit Error Rate (BER). Given that ReRAM devices are nonlinear elements, the nonlinear phenomenon of Stochastic Resonance (SR), which defines that an input disturbance with specific characteristics can improve the total performance of the nonlinear system, is used to reduce the ReRAM cell’s BER. Thus, in this work, the BER of a single ReRAM cell is explored, using the Stanford PKU model, and is improved after the application of specific additive input noise. The power dissipation of the proposed approach is also evaluated and compared with the consideration of higher amplitude writing pulses in the lack of noise, showing that the proposed noiseinduced technique can decrease the BER without the excessive increase of the power dissipation. As a first step, towards the experimental verification of the proposed method, noise-induced measurements on a single fabricated ReRAM device are also performed. Overall, the presented results of the BER reduction with low power dissipation, reaching up to 3:26x less power consumption considering 100 ns writing pulses, are encouraging for ReRAM designers, delivering a circuit-level solution against the device-level problem. This work was supported in part by Spanish MICIU and MINECO under Projects TEC2016-75151-C3-R, TEC2017-90969-EXP and PID2019-103869RB-C3 and in part by FPI-UPC and partially supported by Greece-Russia bilateral joint research project MEM-Q (proj.no./MIS T4∆PΩ-00030/5021467) supported by GSRT, funded by National and European funds.

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Resistive switching devices - memristors - present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

© 2020 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ Resistive switching devices (memristors) constitute an emerging device technology promising for a vari- ety of applications that are currently being studied. In this context, the use of memristors as coupling el- ements of the dynamics of chaotic circuits for adaptive synchronization purposes, was recently proposed and the passive crossbar array was evaluated as target interconnect medium. Nonetheless, memristors may suffer from defects and degradation. Therefore, this work evaluates the impact of memristor switch- ing faults in an adaptive chaotic synchronization scheme, exploring at the same time the fault-tolerance of the crossbar architecture. Moreover, inspired from our observations in the stuck-at-OFF fault analy- sis of the memristive crossbar, some alternative scalable memristive interconnect patterns are suggested, whose performance is found independent of the number of interconnected chaotic circuits, requiring a much smaller number of total memristors than the crossbar array. All simulations are based on an ac- curate physics-based model of a bipolar memristor with filamentary switching mechanism. Based on our results, using the alternative topologies instead of the crossbar array leads to significant savings in the synchronization time that increase with the number of interconnected chaotic units, at the cost of more limited scaling capability and fault-tolerance. This work was supported in part by the Chilean research Grants ANID REDES ETAPA INICIAL 2017 No. REDI170604, ANID FONDECYT INICIACION 11180706, ANID BASAL FB0008, and by the Spanish MINECO and ERDF under Grant TEC2016-75151-C3-2-R.

Electronic version of an article published as [Fernandez, Carlos, Ioannis Vourkas, and Antonio Rubio. "Shortest Path Computing in Directed Graphs with Weighted Edges Mapped on Random Networks of Memristors." Parallel Processing Letters 30.01 (2020): 2050002] [https://doi.org/10.1142/S0129626420500024] © [copyright World Scientific Publishing Company] [https://www.worldscientific.com/worldscinet/ppl] To accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the solution of complex optimization problems. Lately, the solution of the shortest-path problem (SPP) in a two-dimensional memristive grid has been given wide consideration. Some still open problems in such computing approach concern the time required for the grid to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology was extended to support weighted directed graphs. We tried memristor device models with fundamentally different switching behavior to check their suitability for such applications and the impact on the timely detection of the solution. Furthermore, the requirement of binary vs. analog operation of memristors was evaluated. Finally, the memristor network-based computing approach was compared to known algorithmic solutions to the SPP over a large set of random graphs of different sizes and topologies. Our results contribute to the proper development of bio-inspired memristor network-based SPP solvers. This work was supported by the Chilean research grants CONICYT REDES ETAPA INICIAL Convocatoria 2017 No. REDI170604, CONICYT BASAL FB0008, and by the Spanish MINECO and ERDF (TEC2016-75151-C3-2-R).

Memristor networks are capable of low-power, massive parallel processing and information storage. Moreover, they have widely used for a vast number of intelligent data analysis applications targeting mobile edge devices and low power computing. However, till today, one of the major drawbacks resulting to their commercial cumbersome growth, is the fact that the fabricated memristor devices are subject to device-to-device and cycle-to-cycle variability that strongly affects the performance of the memristive network and restricts, in a sense, the utilisation of such systems for real-life demanding applications. In this work, we put effort on increasing the performance of memristive networks by incorporating external additive noise that will be proven to have a beneficial role for the memristor devices and networks. More specifically, we are taking inspiration from the well-known non-linear system phenomenon, called Stochastic Resonance, which alleges that noisy signals with specific characteristics can positively affect the operation of non-linear devices. As such, we are now focusing on the utilisation of the phenomenon on memristor devices in a way that the negative effect of variability is reduced, thus the operation of the whole memristor network is assisted by the increased variability tolerance. The presented results of Bit Error Rate (BER) on a small ReRAM crossbar array sound promising and enable us to further investigate the exploitation of the described phenomenon by memristor-based networks and memories.

©2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology. The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) ´ from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).

Considering the constraints of CMOS technology progress at the nano-domain, memristor technology is one of the preferred alternatives to merge with and substitute CMOS-based memory circuits. At the same time to increase the bandwidth of memories, increase storage density and decrease the interconnection complexity of circuits, multiple-valued logic (MVL) based circuit memories are being introduced as an efficient alternative. As resistive random access memory (ReRAM) is a non-volatile memory and memristor cells allow analog multilevel behavior, they are suitable device to store multiple-level bits of information. Different sources of noise and perturbances may affect the original values of data during the transferring and storing processes. A hybrid scenario based on CMOS and memristor technology is proposed here to recover the stored multiple noisy-perturbed values of resistive random-access memory in an efficient way. To show the correctness of the proposed method, affected images are simulated with Matlab software at system level showing its efficiency.

Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbar- based memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65% in comparison with non-adaptive reconfiguration strategy.

This paper proposes a novel strategy to detect aging in high frequency integrated circuits based on on-line temperature monitoring using built-in differential temperature sensors. To theoretically prove the feasibility of the technique, the paper describes the electro-thermal methodology followed to assert the sensitivity of the temperature sensor's output voltage to track the aging of a 2.4 GHz class A power amplifier.

Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other hand, is a fundamentally nonlinear circuit element, thus susceptible to benefit from SR, which recently came in the spotlight of the emerging technologies potential candidates. However, at this time, the variability exhibited by manufactured memristor devices within the same array constitutes the main hurdle in the road towards the commercialisation of memristor-based memories and/or computing units. Thus, in this paper, memristor SR effects are explored, assuming various memristor models, and SR-based memristance range enhancement, tolerant to device-to-device variability, is demonstrated. Our experiments reveal that SR can induce significant R MAX /R MIN ratio increase under up to 60% variability, getting as high as 3.4× for 29 dBm noise power.

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Since CMOS technology approaches its physical limits, the spotlight of computing technologies and architectures shifts to unconventional computing approaches. In this area, novel computing systems, inspired by natural and mostly nonelectronic approaches, provide also new ways of performing a wide range of computations, from simple logic gates to solving computationally hard problems. Reaction-diffusion processes constitute an information processing method, occurs in nature and are capable of massive parallel and low-power computing, such as chemical computing through Belousov-Zhabotinsky reaction. In this paper, inspired by these chemical processes and based on the wave-propagation information processing taking place in the reaction-diffusion media, the novel characteristics of the nanoelectronic element memristor are utilized to design innovative circuits of electronic excitable medium to perform both classical (Boolean) calculations and to model neuromorphic computations in the same Memristor-RLC (M-RLC) reconfigurable network.

Memristors are being considered as promising devices for highly dense memory systems as well as the potential basis of new computational paradigms. In this scenario, and in relation with data processing, one of the more specific and differential logic functions is the material implication logic also named as IMPLY logic. Many papers have been published in this framework but few of them are related with experimental works using real memristor devices. In the paper authors show the verification of the IMPLY function by using $\mathrm{Ni}/\mathrm{HfO}_{2}/\mathrm{Si}$ manufactured devices and laboratory measurements. The proper behavior of the IMPLY structure (2 memristors) has been shown. The paper also verifies the proper operation of a two-steps IMPLY-based NAND gate implementation, showing the electrical behavior of the circuit in a cycling operation. A new procedure to implement a NAND gate that requires only one step is experimentally shown as well.

In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/pFinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.

The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered 'what is the quantitative effect of the injected energy on the device state?' Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the 'resistance change per energy unit' (dR/dE) can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Cellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like structure. Each such unit, referred as CA cell, performs simplistic computations/processes. However, a network of such identical cells can exhibit nonlinear behavior and be used to model highly complex physical phenomena and processes and to solve problems that are highly complicated for conventional computers. Brain activity has always been considered one of the most complex physical processes and its modeling is of utter importance. This work combines the CA parallel computing capability with the nonlinear dynamics of the memristor, aiming to model brain activity during the epileptic seizures caused by the spreading of pathological dynamics from focal to healthy brain regions. A CA-based confrontation extended to include long-range interactions, combined with the recent notion of memristive electronics, is thus proposed as a modern and promising parallel approach to modeling of such complex physical phenomena. Simulation results show the efficiency of the proposed design and the appropriate reproduction of the spreading of an epileptic seizure.

With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- cells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below $\mathrm {V}_{\mathrm {T}}$ (i.e. sub-threshold).

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant demand for more computational power requires for novel unconventional computing solutions. In this area, the oscillatory internal motion mechanism of slime mould, namely Physarum Polycephalum, could serve as an alternative concept for the design and development of electronic circuits that exploit the memristive dynamics and simple LC contours to deliver solutions for computationally hard to be solved problems. In this direction, this work presents how bio-inspired memristive LC oscillators with a coupling capacitor can be synchronized to perform the functionalities of a biological neuron, also able to execute more complex computations, aiming to model biological neural systems much more advanced than the neuron-less slime mould biological organism. This work proposes a connection between the function mechanism of a simple biological organism and that of complex biological systems, made in a plausible and sufficient manner, towards unconventional computation with memristors.

In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated, but most of the efforts have been just focused on accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is still missing and barely reported yet. In this paper, the time evolution of the memristors involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included.

The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention due to their attractive characteristics such as scalability and CMOS friendly manufacturing. However, similar to any other new technology emergences, having reliability and high performance devices is a challenge, and innovative new techniques are required to make the products attractive and robust enough before entering into the semiconductor market. The research for such crucial reliability concerns and mitigation techniques are ongoing hot topic and the main motivation for this work. Therefore, in this paper, we have studied the origins of RRAM variability and reviewed some of the existing techniques to mitigate its effect at circuit level. To show the relevance of variability in RRAM memories we have further analyzed its impact in the Read/Write memory operation and have presented the memory unreliability that we measure by a parameter as probability of error can be 25% during the read operation and in presence of such resistance variations. In the next phase we have presented a conventional 1T1R memory architecture where we have proposed our reconfiguring strategies to extend the memory lifetime. These reconfiguration strategies utilize a monitoring technique, what we have implemented in order to measure the resistance ratios in RRAM memory cells. Such monitoring approach can detect the highly variability effected and differentiate the bad cells from the good cells; therefore, it can improve the overall RRAM memory reliability.

Trabajo presentado al 6th Workshop on Vision and Language, celebrado en Valencia (España) el 4 de abril de 2017., Finding a product in the fashion world can be a daunting task. Everyday, e-commerce sites are updating with thousands of images and their associated metadata (textual information), deepening the problem. In this paper, we leverage both the images and textual metadata and propose a joint multi-modal embedding that maps both the text and images into a common latent space. Distances in the latent space correspond to similarity between products, allowing us to effectively perform retrieval in this latent space. We compare against existing approaches and show significant improvements in retrieval tasks on a largescale e-commerce dataset.

Trabajo presentado a la International Conference on Computer Vision Workshops (ICCVW), celebrada en Venice (Italy) del 22 al 29 de octubre de 2017., We present an approach to detect the main product in fashion images by exploiting the textual metadata associated with each image. Our approach is based on a Convolutional Neural Network and learns a joint embedding of object proposals and textual metadata to predict the main product in the image. We additionally use several complementary classification and overlap losses in order to improve training stability and performance. Our tests on a large-scale dataset taken from eight e-commerce sites show that our approach outperforms strong baselines and is able to accurately detect the main product in a wide diversity of challenging fashion images., This work is partly funded by the Spanish MINECO project RobInstruct TIN2014-58178-R. A. Rubio is supported by the industrial doctorate grant 2015-DI-010 of the AGAUR.

This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.

Memristors are considered a promising emerging device that may improve some specific applications, like memories, or make feasible new ones, mainly alternative computing architectures. However, it is not a mature technology and their characteristics can vary significantly depending on their structures. Also, variability and reliability might suppose an important issue in some applications. In this paper, a chalcogenide memristor is studied and their main parameters are extracted. Then, it's discused how their properties can affect two applications: a memory circuit and a digital computing alternative, the logic implication technique.

Trabajo presentado a la IEEE International Conference on Image Processing (ICIP), celebrada en Beijing (China) del 17 al 20 de septiembre de 2017., Finding a product in the fashion world can be a daunting task. Everyday, e-commerce sites are updating with thousands of images and their associated metadata (textual information), deepening the problem, akin to finding a needle in a haystack. In this paper, we leverage both the images and textual meta-data and propose a joint multi-modal embedding that maps both the text and images into a common latent space. Distances in the latent space correspond to similarity between products, allowing us to effectively perform retrieval in this latent space, which is both efficient and accurate. We train this embedding using large-scale real world e-commerce data by both minimizing the similarity between related products and using auxiliary classification networks to that encourage the embedding to have semantic meaning. We compare against existing approaches and show significant improvements in retrieval tasks on a large-scale e-commerce dataset. We also provide an analysis of the different metadata., This work is partly funded by the Spanish MINECO project RobInstruct TIN2014-58178-R, by the ERA-Net Chistera project I-DRESS PCIN-2015-147 and by the EU project iAEROARMS H2020-ICT-2014-1-644271. A.Rubio is supported by the industrial doctorate grant 2015-DI-010 of the AGAUR.

Diabetes mellitus is a disease that affects to hundreds of millions of people worldwide. Maintaining a good control of the disease is critical to avoid severe long-term complications. In recent years, several artificial pancreas systems have been proposed and developed, which are increasingly advanced. However there is still a lot of research to do. One of the main problems that arises in the (semi) automatic control of diabetes, is to get a model explaining how glycemia (glucose levels in blood) varies with insulin, food intakes and other factors, fitting the characteristics of each individual or patient. This paper proposes the application of evolutionary computation techniques to obtain customized models of patients, unlike most of previous approaches which obtain averaged models. The proposal is based on a kind of genetic programming based on grammars known as Grammatical Evolution (GE). The proposal has been tested with in silico patient data and results are clearly positive. We present also a study of four different grammars and five objective functions. In the test phase the models characterized the glucose with a mean percentage average error of 13.69%, modeling well also both hyper and hypoglycemic situations.

The R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results with a majority criterion. In this analytic study, we extend this conventional approach by introducing the time dimension in the RMR design. Indeed, the asynchronous nature of future nanoelectronic computing systems is taken into account by introducing the partially asynchronous RMR (pA-RMR) structure whose main feature is to detect the arrival of each input signal from the replicas based on the use of tokens. The voter behavior is modified in such a way that it sets the output result after a determined number of token arrivals. By doing this, we are adding a second degree of freedom to the RMR structure, which not only has a configurable size (R replicas), but also allows modifying the number of tokens it waits before giving an output. As a consequence of this seemingly simple change, we are able to exploit new possibilities of this redundant structure. This second degree of freedom allows choosing between system reliability and performance during operation. The number of available replicas in the pA-RMR architecture determines the maximum reliability achievable, while the voting policy allows us to adapt the structure to different design requirements and achieve the desired balance between reliability and performance.

In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative to the bulk one. We observe an improvement in its behavior when IG and SG FinFETs are properly mixed, since together they provide a relevant increase in the memory circuit retention time. Moreover, our FinFET cell shows larger variability robustness, better performance at low supply voltage, and higher tolerance to elevated temperatures.

It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.

FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltagecontrolled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memristive circuits and prove its synaptic properties in a small associative memory via a perceptron ANN.

Trabajo presentado a la 23rd International Conference on Pattern Recognition, celebrada en Cancún (México) del 5 al 8 de diciembre de 2016., We propose a new superpixel algorithm based on exploiting the boundary information of an image, as objects in images can generally be described by their boundaries. Our proposed approach initially estimates the boundaries and uses them to place superpixel seeds in the areas in which they are more dense. Afterwards, we minimize an energy function in order to expand the seeds into full superpixels. In addition to standard terms such as color consistency and compactness, we propose using the geodesic distance which concentrates small superpixels in regions of the image with more information, while letting larger superpixels cover more homogeneous regions. By both improving the initialization using the boundaries and coherency of the superpixels with geodesic distances, we are able to maintain the coherency of the image structure with fewer superpixels than other approaches. We show the resulting algorithm to yield smaller Variation of Information metrics in seven different datasets while maintaining Undersegmentation Error values similar to the state-of-the-art methods., This work is partly funded by the Spanish MINECO project RobInstruct TIN2014-58178-R, by the ERA-Net Chistera project I-DRESS PCIN-2015-147 and by the EU project AEROARMS H2020-ICT-2014-1-644271. A. Rubio is supported by the industrial doctorate grant 2015-DI-010 of the AGAUR.

The articles in this special section focus on new technological innovationsin EDA design. The constant evolution of electronic systems has been fueled by the continuous and tremendous progress of silicon technology manufacturing. Since 1960, when the first MOS transistor was manufactured with dimensions around 50 cm, process technology has been constantly enhancing until the current 22-nm MOS technology. Every two years a new process generation roughly doubles the device density, following what is known as Moore's law. Besides, every new generation offers faster devices that consume less energy by operation. This has put in the hands of architects more powerful and energy-efficient building blocks on top of which they have designed more effective architectures with increasing capabilities. Silicon MOSFETs have been the workhorse devices for information technologies during all these last decades. However, these technology advances have to deal with important challenges coming from physical limitations of the underlying transistors, which are affected by severe manufacturing process parameters variability and aging caused by electrical degradation of materials due to the intense electrical stress during operation.

Diabetes mellitus is a disease that affects to hundreds of million of people worldwide. Maintaining a good control of the disease is critical to avoid severe long-term complications. One of the main problems that arise in the (semi) automatic control of diabetes, is to get a model explaining how glucose levels in blood vary with insulin, food intakes and other factors, fitting the characteristics of each individual or patient. In this paper we compare genetic programming techniques with a set of classical identification techniques: classical simple exponential smoothing, Holt's smoothing (linear, exponential and damped), classical Holt and Winters methods and auto regressive integrated moving average modeling. We consider predictions horizons of 30, 60, 90 and 120 minutes. Experimental results shows the difficulty of predicting glucose values for more than 60 minutes and the necessity of adapt GP techniques for those dynamic environments.

Trabajo presentado al ICRA celebrado en Seattle (US) del 26 al 30 de mayo de 2015., We propose a robust and efficient method to estimate the pose of a camera with respect to complex 3D textured models of the environment that can potentially contain more than 100, 000 points. To tackle this problem we follow a top down approach where we combine high-level deep network classifiers with low level geometric approaches to come up with a solution that is fast, robust and accurate. Given an input image, we initially use a pre-trained deep network to compute a rough estimation of the camera pose. This initial estimate constrains the number of 3D model points that can be seen from the camera viewpoint. We then establish 3D-to-2D correspondences between these potentially visible points of the model and the 2D detected image features. Accurate pose estimation is finally obtained from the 2D-to-3D correspondences using a novel PnP algorithm that rejects outliers without the need to use a RANSAC strategy, and which is between 10 and 100 times faster than other methods that use it. Two real experimentsdealing with very large and complex 3D models demonstrate the effectiveness of the approach., This work has been partially funded by the Spanish Ministry of Economy and Competitiveness under projects ERANet Chistera project ViSen PCIN-2013-047, PAU+ DPI2011-27510 and ROBOT-INT-COOP DPI2013-42458-P, and by the EU project ARCAS FP7-ICT-2011-28761.

Current RFIC test practices perform system-level verification through specific functional validation. Structural testing, although widely accepted for digital and analog generic ICs, is not adopted in this domain due to the lack of appropriate fault models. Another important reason is the impossibility of embedding test-mode circuitry within the RF blocks because of parasitic component disturbances. This work discusses the feasibility of complementing functional tests with structural methods by using thermal testing. The benefits reside in the intrinsic electrical loadless property of the technique and the impact of many defects on the circuit temperature. The analysis focuses on the possibilities of detecting defects that escape functional testing, and practical implementation issues.

Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a memory data path. In our study, the impact of variations in the cell block is the largest measured, as it is usually designed with the minimum device dimensions. Moreover, we observe a significant influence of the device type (p/nMOS) used to implement the memory cell in terms of delay and variability robustness. Keywords—variability, DRAM, delay, temperature.

Diabetes mellitus is a disease that affects to hundreds of millions of people worldwide. Maintaining a good control of the disease is critical to avoid severe long-term complications. In recent years, a lot of research has been made to improve the quality of life of the diabetic patient, especially in the automation of glucose level control. One of the main problems that arises in the (semi) automatic control of diabetes, is to obtain a model that explains the behavior of blood glucose levels with insulin, food intakes and other external factors, fitting the characteristics of each individual or patient. Recently, Grammatical Evolution (GE), has been proposed to solve this lack of models. A proposal based on GE was able to obtain customized models of five in-silico patient data with a mean percentage average error of 13.69%, modeling well also both hyper and hypoglycemic situations. In this paper we have extended the study of Error Grid Analysis (EGA) to prediction models in up to 8 in-silico patients. EGA is commonly used in Endocrinology to test the clinical significance of differences between measurements and real value of blood glucose, but has not been used before as a metric in obtention of glycemia models.

3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.

This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE.

An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an I/sub DDQ/ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's. >

In this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented to execute task requirements in a dynamic, flexible, efficient and adaptive way. In this technique not only the logic functions are modifiable (as in the case of Field Programmable Gate Array, FPGA) but also the physical position of the logic elements that form the circuit. Furthermore, a new technologic strategy that allows implementing large crossbars of memFETs is introduced. The memFET is an electrically reconfigurable field effect and resistive switching device that can be used to perform logic functions and memory blocks. Into an appropriate structure such as a crossbar array, memFET allows the dynamic logic reconfiguration of the crossbar and simplify both the design and the implementation of computing hardware.

In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment

In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce standby leakage power in first level data-caches under process variations. Accessed physical arrays are forward body biased (FBB) to improve latency while idle (unaccessed) arrays are reverse body biased (RBB) for reducing standby leakage power. The bias voltage to be applied is computed at design time and updated at run-time to counter the negative effects of process variations. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. A sensor-like hardware mechanism measures the variation in latency and leakage at run-time and this measurement is used to update the bias voltage. The backbone of the hardware used for measurement is a three-transistor one-diode(3T1D)DRAM cell embedded into a regular cache array. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage profiles. Our technique reduces leakage energy consumption and access latency of the cache on an average by 20% & 18% respectively. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that range from nano-scaled complementary metal–oxide–semiconductor (CMOS) devices through recent developments in nano capacitors and AlGaAs/GaAs devices. The contributors are world-renowned experts from academia and industry from around the globe. The handbook explores current research into potentially disruptive technologies for a post-CMOS world. These include: Nanoscale advances in current MOSFET/CMOS technology Nano capacitors for applications such as electronics packaging and humidity sensors Single electron transistors and other electron tunneling devices Quantum cellular automata and nanomagnetic logic Memristors as switching devices and for memory Graphene preparation, properties, and devices Carbon nanotubes (CNTs), both single CNT and random network Other CNT applications such as terahertz, sensors, interconnects, and capacitors Nano system architectures for reliability Nanowire device fabrication and applications Nanowire transistors Nanodevices for spintronics The book closes with a call for a new generation of simulation tools to handle nanoscale mechanisms in realistic nanodevice geometries. This timely handbook offers a wealth of insights into the application of nanoelectronics. It is an invaluable reference and source of ideas for anyone working in the rapidly expanding field of nanoelectronics.