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This paper presents novel pulse based techniques initially intended to implement signal processing functions such as analogue and mixed-signal filters, data converters and amplitude modulators. Field programmable devices using these techniques have been implemented and used on a demonstration board to implement analogue and mixed-signal arrays. The rich mix of analogue and digital functionality provided by Palmo systems combined with the fact that they may accept random configuration bit streams makes them most attractive as platforms for evolvable hardware. [ABSTRACT FROM AUTHOR]

Inference process plays an important role in the realisation of expert systems. In this paper it is shown that chemical reactions may by used to perform molecular inference according to the algorithm of forward chaining. This method is accomplished by an adequate interpretation of inorganic chemical compounds and unidirectional reactions. In our approach premise clauses are represented by the reactants while conclusion clauses are represented by the products of reaction. Different inorganic compounds and reactions have been discussed with respect to their utility for the molecular inference. Special attention is focused on qualitative chemistry and a number of reactions has been taken into account. Experimental results demonstrating application of these reactions in expert systems are provided. [ABSTRACT FROM AUTHOR]

Most work in evolutionary robotics used a neural net approach for control of a mobile robot. Genetic programming has mostly been used for computer simulations. We wanted to see if genetic programming is capable to evolve a hierarchical control architecture for simple reactive navigation on a large physical mobile robot. First, we evolved hierarchical control algorithms for a mobile robot using computer simulations. Then we repeated one of the experiments with a large physical mobile robot. The results achieved are summarized in this paper. [ABSTRACT FROM AUTHOR]

POLYP is a second generation, massively parallel reconfigurable computer based on micro-reconfigurable Field Programmable Gate Arrays (Xilinx XC6000) with a high density of additional distributed memory under local control and broad-band dynamically reroutable optical interconnect technology. Inspired by and designed to study the dynamical self-organization of distributed molecular biological systems using the programmable matter paradigm (like its predecessor NGEN), the new hardware allows the study of large interacting evolving populations of functional design elements in hardware. POLYP includes 144 FPGAs and 400 MB of high speed distributed memory on twelve 18-layer extended VME boards each interconnected via 2 crossbars to 80 unidirectional optical fibers. It is extendable to 20 boards in a single chassis and further to asynchronous multiple host operation. Local reconfiguration of the hardware is mediated by an intermediate hierarchical level of distributed macro-reconfigurable FPGAs, so that the machine is capable of simultaneously evolving functional circuits and their binary representation under user-configurable local control. The process of hierarchical configuration reached the fine-grained level in November 1997, and this paper reports a first experiment in hardware evolution performed with the machine. In contrast with previous evolvable hardware examples, the example is designed to explore the evolution of interconnection structures. As a first step with the new hardware, it by no means yet exploits the powerful potential of the machine. Just as NGEN allowed the study of spatially distributed epigenetic effects in interacting populations of molecules in user-configurable hardware, POLYP allows the study of such effects with individuals dynamically reconfiguring the local hardware. [ABSTRACT FROM AUTHOR]

This article presents a software routing algorithm used to increase fault tolerance of a large-scale MIMD computer based on an isochronous crossbar network. The routing algorithm is completed with a placement algorithm that uses an evolutionary approach that allows dynamic reconfigurations of the task-processor mapping when a fault is detected. [ABSTRACT FROM AUTHOR]

In this paper we shall address the paradigms of evolutionary and self-repairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose microcontroller. Furthermore, the programmable digital section has been designed including a flexible and fast dynamic reconfiguration scheme. These properties provide an efficient framework for tackling the specific features posed by the emerging field of evolutionary computation. We shall demonstrate this fact by means of two different case studies: a self-repairing strategy for digital systems, suitable for applications in environments exposed to radiation, and an efficient implementation scheme for evolving parallel cellular machines. [ABSTRACT FROM AUTHOR]

We propose a new general-purpose computer architecture based on programmable logic. It consists of a dual-structured array of cells accommodating a fixed "built-in part" and a freely programmable "plastic part". We call this composition the "Plastic Cell Architecture" (PCA). The built-in part with its fully connective two-dimensional mesh structure serves as a communication platform based on the cellular automata model. It is responsible for the configuration of the plastic part which implements a sea of logic gates similar to programmable devices (FPGA). The key point of our architecture is dynamic, distributed object instantiation during runtime. An object can encapsulate data and/or behavior and communicates with other objects through a unique type of message passing implemented in hardware. Thus, PCA combines the merits of fine grained, high performance hardware implementation and the dynamic memory allocation capabilities of software. [ABSTRACT FROM AUTHOR]

The FPPA concept has been developed in 1996, to address two main goals. The first one is to develop massively parallel processing unit arrays that require large chip areas, and the second one is to obtain a good substratum for evolutive algorithms. In such algorithms, phenotype evaluation is the most computing intensive task, so that if such kind of architecture is scaled beyond the conventional limits, the efficiency is significantly improved. However, several problems occur when chip size increases, as clock-skew and fabrication defects. The proposed solution is an array of cells, in which each cell contains a small low-power processor and a hierarchy of memories. The array tolerates defects by self-test and autonomous reconfiguration. Clock-skews are compensated by interconnecting the cells through an asynchronous protocol communication network. The FPPA is a single-chip MIMD machine that should be considered as a very coarse grain FPGA. [ABSTRACT FROM AUTHOR]

In order to understand the dynamic interactions of autonomous robots with their environments, the flow of the sensory information perceived by a real mobile robot Khepera was analyzed with the return map. The plot of Xn+1 v.s. Xn of chaotic time series Xn, called the return map, have been widely used to reveal the hidden structure. A real mobile robot Khepera was evolved in three different environments with various levels of complexity. The fitness function of GA operations included the complexity measure of the control structure, i.e., individuals with a simpler structure obtained a higher score. The evolution lead to develop the robot with the minimal structure sufficient to live and perform tasks in the given environment. The return maps of these robots differed each other considerably. However, when the robot evolved in the most complex environment was asked to navigate in the other two environments, the return maps obtained there were similar to (or a substructure of) the one in the most complex environment. These results indicated that the autonomous robot behaved such a way that the flow of sensory information did not depend much on the environment where he situated but largely on the one where he had evolved. [ABSTRACT FROM AUTHOR]

An image segmentation algorithm, based on Pulse-Coupled Neural Networks, was implemented in silicon. We aimed at simplifying neuron hardware implementation while maintaining segmentation efficiency. Some algorithmic tricks have then been added, improving the results. The main components of the underlying neuron architecture are a single 8 bits register, a simple incrementer, and some glue logic. A prototype, using a data flow architecture, implementing a 64x64 neuron array, and based on a 0.2 Μm CMOS SOI technology, will be released in 1998. A 64x64 segmentation is expected in less than 50 Μs. [ABSTRACT FROM AUTHOR]

A modified back-propagation (BP) algorithm for the development of autonomous robots was proposed, and applied to a real mobile robot Khepera. Coefficients of a multi-layered neural network (NN), that determined the sensor-motor reflex of the robot, were first set randomly, and the robot was allowed to behave in an environment for some time. Sets of the sensor-motor values were continuously sampled during the free-moving period, and each set was evaluated by the behavior that occurred after the sampling by using an evaluation function. The set obtained the highest score was selected for each sensor pattern, and used to train the NN with BP. By repeating the above procedures, the robot obtained the adaptive behavior for the given environment in accordance with the evaluation function. The time needed for Khepera to acquire the ability of navigation was approximately one tenth of the conventional genetic evolution. [ABSTRACT FROM AUTHOR]

This paper reports on ongoing attempts to find an efficient and effective representation for the binary signaling of ATR's CAM-Brain Machine (CBM), using the so-called "CoDi-1Bit" model. The CBM is an Field Programmable Gate Array (FPGA) based hardware accelerator which updates 3D cellular automata (CA) cells at the rate of 100 billion a second, allowing a complete run of a genetic algorithm with tens of thousands of CA based neural net circuit growths and hardware compiled fitness evaluations, all in about 1 second. It is hoped that using such a device, it will become practical to evolve 10,000s of neural net modules and then to assemble them into humanly defined RAM based artificial brain architectures which can be run by the CBM in real time to control robots, e.g. a robot kitten. Before large numbers of modules can be assembled together, it is essential that the individual modules have a good functionality and evolvability. The "CoDi-1Bit" CA based neural network model uses 1 bit binary signaling, so a representation needs to be chosen based on this fact. This paper introduces and discusses the merits and demerits of a representation that we call "Spike Interval Information Coding" (SIIC). Simulation results using the SIIC representation method to evolve time dependent waveforms and simple functional modules are presented. The results indicate the suitability of the SIIC representation method to decode the bit streams generated by the CA based neural networks. [ABSTRACT FROM AUTHOR]

Learning in artificial neural networks is often cast as the problem of "teaching" a set of stimulus-response (or input-output) pairs to an appropriate mathematical model which abstracts certain known properties of neural networks. A paradigm which has been developed independently of neural network models are genetic algorithms (GA). In this paper we introduce a mathematical framework concerning the manner in which genetic algorithms can learn, and show that gradient descent can be used in this frameork as well. In order to develop this theory, we use a class of stochastic genetic algorithms (GA) based on a population of chromosomes with mutation and crossover, as well as fitness, which we have described earlier in [18]. [ABSTRACT FROM AUTHOR]

The field of evolvable hardware or bio-inspired hardware holds the promise of automatically engineering complex electronic systems that remain adaptive during use. A growing number of experiments along these lines have been performed recently, mostly using off-the-shelf hardware or straightforward extensions of building blocks used by human engineers [1] [2]. In this paper we use the POE (Phylogeny Ontogeny Epigenesis) framework of bio-inspired hardware systems [3] and restrict evolutionary search and development considerations to pure hill-climbing search only, in order to develop some theory around evolution of electronic circuits. From this theory a new analog re-configurable hardware architecture is proposed for use in evolvable hardware. The hardware is a context switchable analog computer which can implement any general non-linear dynamic system on the level of the vector field representation. The optimization algorithm is a bio-inspired "molding" of the state-space description of the system. We call this novel hardware/ optimization algorithm platform the "modeling clay" approach to bio-inspired electronic hardware. [ABSTRACT FROM AUTHOR]

The anatomy of the insect brain provides insights to neural architectures and visual processing algorithms which serve as blueprints for neuromimetic silicon chip designs. Selective attention reduces the amount of computation required by a biological system navigating through an information rich environment. In the insect visual system we see an example of task-specific sensor optimization for the detection of a topological invariant, the focus of expansion of the optic flow. A description of those regions of the optic lobe concerned with flow-field analysis is presented and this is followed by a description of a simple neural subsystem capable of detecting such a focus. This information is used in a feedback control system involving the peripheral sensors to gate object tracking and orienting systems. This robust and simple system is an ideal candidate for implementation in evolving silicon based vision systems. [ABSTRACT FROM AUTHOR]

There is considerable evidence that pinna (external ear) shape plays a crucial role in the localisation, especially along the vertical dimension, of targets by echolocating animals. However, because of the complexity of the relation between pinna shape and localisation performance it is very difficult to design them so that the echolocator achieves specific localisation characteristics. Hence, we have developped a genetic algorithm (GA) which in conjunction with an acoustic echo simulator allows us to evolve desirable pinna shapes instead of having to design them. We use this method to evolve a rudimentary pinna that allows an echolocator, using a broadband call, to determine the vertical component of a target's location by comparing the measured intensities at different frequencies. [ABSTRACT FROM AUTHOR]

One of the central challenges of evolutionary computing and artificial life research is to establish a methodology for building very large complex system which has functional structures. Although it is increasingly recognized that the use of developmental process is the promising approach, none of existing method can create complex structures involving large scale repetitive subunits which characterize functional biological and artificial systems, such as brain, animal body, memory chips. In this paper, we present a powerful method of developing very complex structures based on a grammar-based approach. The introduction of novel meta-node and associated operations is the essential feature of the method. We demonstrate the strength of the method by actually developing the network topologies identical to human receptive fields of skin for touch stimuli and cerebeller cortex. [ABSTRACT FROM AUTHOR]

Embryonics' proposal is to construct arrays of processing elements with self-diagnosis and self-reconfiguration abilities able to tolerate the presence of failing cells in the same fashion as natural cellular systems do. Self-healing mechanisms found in nature and the implicit redundancy of cellular architectures constitute the foundations of embryonic systems' fault tolerance properties. It will be shown in this paper how by incorporating the biological concepts of chromosome and gene, the complexity of the MUXTREE embryonic architecture can be simplified, in comparison with the previous version. It is argued that by assuming a broader meaning for the concept of evolution it possible to classify embryonic arrays and other adaptable systems as evolvable. [ABSTRACT FROM AUTHOR]

A fundamental process in nature is that of ontogeny, whereby a single mother cell—the zygote—gives rise, through successive divisions, to a complete multicellular organism. Over the years such developmental processes have been studied using different models, two of which shall be considered in this paper: L-systems and cellular automata. Each of these presents distinct advantages: L-systems are naturally suited to model growth processes, whereas if one wishes to consider physical aspects of the system, e.g., as pertaining to actual implementation in hardware, then an inherently spatial model is required—hence the cellular automaton. Our goals herein are: (1) to show how L-systems can be used to specify growing structures, and (2) to explore the relationship between L-systems and cellular automata. Specifically, we shall consider the case of membrane formation, whereby a grid of artificial molecules is divided into cells. [ABSTRACT FROM AUTHOR]

The ontogenetic development of living beings suggests the design of a new kind of multicellular automaton endowed with novel quasi-biological properties: self-repair and self-replication. In the framework of the Embryonics (embryonic electronics) project, we have developed such an automaton. Its macroscopic architecture is defined by three features: multicellular organization, cellular differentiation, and cellular division which are described in a companion paper [5]. In order to cope with the complexity of real problems, the cell is itself decomposed into an array of smaller elements, the molecules, themselves defined by three features: multimolecular organization, self-test and self-repair, and finally cellular self-replication, which is the basis of the macroscopic process of cellular division. These microscopic properties are illustrated by the example of an up-down counter. Finally, we propose a design methodology based on three successive configurations of the basic molecular tissue, a novel FPGA. These configurations are analogous to the operation of three kinds of genetic information: the polymerase, ribosomic, and operative genomes. [ABSTRACT FROM AUTHOR]

The ontogenetic development of living beings suggests the design of a new kind of multicellular automaton endowed with novel quasi-biological properties: self-repair and self-replication. In the framework of the Embryonics (embryonic electronics) project, we have developed such an automaton. Its macroscopic architecture is defined by three features: multicellular organization, cellular differentiation, and cellular division. Through a simple example, a stopwatch, we show that the artificial organism possesses the macroscopic properties of self-replication (cloning) and self-repair. In order to cope with the complexity of real problems, the cell will be decomposed into an array of smaller elements, the molecules, themselves defined by three features: multimolecular organization, self-test and self-repair, and finally cellular self-replication, which is the basis of the macroscopic process of cellular division. These microscopic properties are the subject of a companion paper [9]. [ABSTRACT FROM AUTHOR]

This paper focuses on characteristics and applications of evolvable hardware (EHW) to space systems. The motivation for looking at EHW originates in the need for more autonomous adaptive space systems. The idea of evolvable hardware becomes attractive for long missions when the hardware looses optimality, and uploading new software only partly alleviates the problem if the computing hardware becomes obsolete or the sensing hardware faces needs outside original design specifications. The paper reports the first intrinsic evolution on an analog ASIC (a custom analog neural chip), suggests evolution of dynamical systems in state-space representations, and demonstrates evolution of compression algorithms with results better than the best-known compression algorithms. [ABSTRACT FROM AUTHOR]

Our work focuses on the use of artificial evolution in Computer Aided Design (CAD) of electronic circuits. Artificial evolution promises to be an important tool for analog CAD development, due to the nature of this task, which has been proven to be much less amenable for standard tools than its digital counterparts. Analog design relies more on the designer's experience than on systematic rules or procedures. The recent appearance of Field Programmable Analog Arrays (FPAAs) allows evolution to be performed in real silicon, which opens new possibilities to the field. Our work addresses the evolution of amplifiers and oscillators, through the use of a standard simulator and a programmable analog circuit respectively. Furthermore, the issue of the implementability of the circuits evolved in simulation is also examined. [ABSTRACT FROM AUTHOR]

The basic properties of programmable analogue arrays are described and the problem of quantifying the fitness of an analogue circuit is discussed. A set of blocks appropriate for use in an evolutionary algorithm is described and results presented showing how an evolutionary algorithm using these blocks can learn to produce a given input-output characteristic. Finally an example is presented showing how the evolutionary algorithm can exploit any looseness in the specification of the desired characteristic. [ABSTRACT FROM AUTHOR]

This paper describes an analogue EHW (Evolvable Hardware) chip for Intermediate Frequency (IF) filters, which are widely used in cellular phones. When analogue Integrated Circuits (ICs) and Large-Scale Integrated Circuits (LSIs) are manufactured, the values of the analogue circuit components, such as resistors or capacitors, often vary from the precise design specifications. Analogue LSIs with such defective components can not perform at required levels and thus have to be discarded. However, the chip proposed in this paper can correct these discrepancies in the values of analogue circuit components by genetic algorithms (GAs). Simulations have shown that 95% of the chips can be adjusted to satisfy the specifications of the IF filters. Using this analogue EHW chip has two advantages, namely, (1) improved yield rates and (2) smaller circuits, which can lead to cost reductions and efficient implementation of LSIs. The chip is scheduled to appear in the fourth quarter of 1998. [ABSTRACT FROM AUTHOR]

We present a method of evolving analog electronic circuits using a linear representation and a simple unfolding technique. While this representation excludes a large number of circuit topologies, it is capable of constructing many of the useful topologies seen in hand-designed circuits. Our system allows circuit size, circuit topology, and device values to be evolved. Using a parallel genetic algorithm we present initial results of our system as applied to two analog filter design problems. The modest computational requirements of our system suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation. [ABSTRACT FROM AUTHOR]

Hardware evolution methodologies come into their own in the construction of real-time adaptive systems. The technological requirements for such systems are not only high-speed evolution, but also steady and smooth evolution. This paper shows that the Progressive Evolution Model (PEM) and Diploid chromosomes contribute toward satisfying these requirements in the hardware evolutionary system AdAM (Adaptive Architecture Methodology). Simulations of an artificial ant problem using four combinations of two wets of variables — PEM vs. non-PEM, and Diploid AdAM vs. Haploid AdAM — show that the Diploid-PEM combination overwhelms the others. [ABSTRACT FROM AUTHOR]

This paper describes a data compression system using Evolvable Hardware (EHW) for digital color electrophotographic (EP) printers. EP printing is an important technology within digital printing, which is currently having a significant impact on the printing and publishing industry. Although, it requires data-compression to reduce the cost for transferring and storing large EP images, traditional techniques can not handle this data-compression well. This paper explains how EHW can be used as a compression system. EHW can change the compression method according to the characteristics of the image. The proposed EHW-based compression system can compress approximately twice as much data as JBIG, the current international standard. [ABSTRACT FROM AUTHOR]

This work takes a different approach to synthesize a synchronous sequential logic circuit. The input of the synthesizer is a partial input/output sequence. This type of specification is not suitable for conventional synthesis methods. Genetic Algorithm (GA) was applied to synthesize the desired circuit that performs according to the input/output sequences. GA searches for circuits that represent the desired state transition function. Additional combination circuits that map states to the corresponding outputs are synthesized by conventional methods. The target of our synthesis is a type of registered Programmable Array Logic which is commercially available as GAL. We are able to synthesize various types of synchronous sequential logic circuit such as counter, serial adder, frequency divider, modulo-5 detector and parity checker. [ABSTRACT FROM AUTHOR]

Cellular Programming is a model of co-evolving dissipative systems which absorb information and dissipate the useless information about the fitness landscapes on which co-evolution is performed. The information convection in the population determines a dissipative structure of the co-evolving non-uniform cellular automata which depends on how far from equilibrium the system is. We show that Cellular Programming is capable of demonstrating an adaptive behaviour somewhere between perfect order and complete disorder where the dissipative structure of co-evolving non-uniform cellular automata is complex. [ABSTRACT FROM AUTHOR]

In this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) combinational circuits is proposed for the first time. In comparison with the decomposition techniques used for synthesis of combinational circuits previously employed, this new approach is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g. singlecontrol MV multiplexer called T-gate). The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The experimental results show how the success of genetic algorithm depends on the number of columns, the number of rows in circuit structure and levels-back parameter (the number of columns to the left of current cell to which cell input may be connected). We show that the choice of the set of MV gates used radically affects the chances of successful evolution (in terms of number of 100% functional solutions found). [ABSTRACT FROM AUTHOR]

We use evolutionary search to find automatically electronic circuits that toggle an output line at, or close to, a given target frequency. Reconfigurable hardware in the form of field-programmable gate arrays—as opposed to circuit simulation—computes the fitness of a circuit which guides the evolutionary search. We find empirically that oscillating circuits can be evolved that closely approximate some of the supplied target frequencies. Our evolved oscillators alias a harmonic of the target frequency to satisfy the fitness goal. Frequencies of the evolved oscillators were sensitive to temperature and to the physical piece of silicon in which they operate. We posit that such sensitivities may have negative implications for demanding applications of reconfigurable hardware and positive implications for adaptive computing. [ABSTRACT FROM AUTHOR]

Evolvable Hardware (EHW) has been proposed as a new method for designing systems for complex real world applications. One of the problems has been that only small systems have been evolvable. This paper indicates some of the aspects in biological systems that are important for evolving complex systems. Further, a divide-and-conquer scheme is proposed, where a system is evolved by evolving smaller subsystems. Experiments show that the number of generations required for evolution by the new method can be substantially reduced compared to evolving a system directly. However, there is no lack of performance in the final system. [ABSTRACT FROM AUTHOR]

The study of intrinsic hardware evolution relies heavily on commercial FPGA devices which can be configured in real time to produce physical electronic circuits. Use of these devices presents certain drawbacks to the researcher desirous of studying fundamental principles underlying hardware evolution, since he has no control over the architecture or type of basic configurable element. Furthermore, analysis of evolved circuits is difficult as only external pins of FPGAs are accessible to test equipment. After discussing current issues arising in intrinsic hardware evolution, this paper presents a new test platform designed specifically to tackle them, together with experimental results exemplifying its use. The results include the first circuits to be evolved intrinsically at the transistor level. [ABSTRACT FROM AUTHOR]

An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16 bit address space into an 8 bit one. This circuit, based on FPGAs, is readily applicable to the design of set-associative cache memories. Possible use the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed. [ABSTRACT FROM AUTHOR]

In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. We examine the effectiveness of evolving circuit functionality by using randomly chosen examples taken from the truth table. We consider the merits of a cell architecture in which functional cells alternate with routing cells and compare this with an architecture in which any cell can implement a function or be merely used for routing signals. It is noteworthy that the presence of elitism significantly improves the Genetic Algorithm performance. [ABSTRACT FROM AUTHOR]

‘Unconstrained intrinsic hardware evolution' allows an evolutionary algorithm freedom to find the forms and processes natural to a reconfigurable VLSI medium. It has been shown to produce highly unconventional but extremely compact FPGA configurations for simple tasks, but these circuits are usually not robust enough to be useful: they malfunction if used on a slightly different FPGA, or at a different temperature. After defining an ‘operational envelope' of robustness, the feasibility of performing fitness evaluations in widely varying physical conditions in order to provide a selection-pressure for robustness is demonstrated. Preliminary experimental results are encouraging. [ABSTRACT FROM AUTHOR]

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced. [ABSTRACT FROM AUTHOR]

In recent years we are witness to a growing number of researchers who are interested in novel computational systems based on principles that are entirely different than those of classical computers. Though coming from disparate domains, their work shares a common computational philosophy, which I call cellular computing. Basically, cellular computing is a vastly parallel, highly local computational paradigm, with simple cells as the basic units of computation. It aims at providing new means for doing computation in a more efficient manner than other approaches (in terms of speed, cost, power dissipation, information storage, quality of solutions), while potentially addressing much larger problem instances than was possible before—at least for some application domains. This paper provides a qualitative exposition of the cellular computing paradigm, including sample applications and a discussion of some of the research issues involved. [ABSTRACT FROM AUTHOR]

Parallel evolutionary algorithms, studied to some extent over the past few years, have proven empirically worthwhile—though there seems to be lacking a better understanding of their workings. In this paper we concentrate on cellular (fine-grained) models, presenting a number of statistical measures, both at the genotypic and phenotypic levels. We demonstrate the application and utility of these measures on a specific example, that of the cellular programming evolutionary algorithm, when used to evolve solutions to a hard problem in the cellular-automata domain, known as synchronization. [ABSTRACT FROM AUTHOR]

The field of artificial life (Alife) is replete with documented instances of emergence, though debate still persists as to the meaning of this term. In the absence of a formal definition, researchers in the field would be well served by adopting an emergence certification mark which would garner approval from the Alife community. We propose an emergence test, consisting of three criteria—design, observation, and surprise—for conferring the emergence label. [ABSTRACT FROM AUTHOR]