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Digital audio sensors have been used in microphone-embedded portable electronics. This paper shows a mixed-signal adaptive readout ASIC for digital audio sensor, which includes a programmable-gain-amplifier, a switched-capacitor sigma-delta modulator, digital signal processing, and power management circuits. The digital part comprises a digital low-pass filter, a digital-gain-compensation and a digital automatic-gain-controller. The clear advantage of this system is to obtain high signal-to-noise ratio (SNR) and wide input range simultaneously. In addition, both a normal operation mode and a sleep mode are realized to address a flexible current budget. The ASIC is fabricated in a 0.18-um CMOS process. Experimental results show the expected adaptive readout function over the input range from 94 to 136 dB SPL. In the normal mode, a system SNR of 68 dB (A-weighted) at 1 kHz 94 dB SPL input is achieved under 600 uA. Further, an impressive acoustic overload point (AOP) of 136 dB SPL is guaranteed. In the standby condition, the sleep mode with current less than 20 uA is obtained, so that the battery life can be extended. Compared to other existing solutions, this adaptive readout ASIC shows the best combination of achievable SNR, AOP and current budget for digital audio sensors. [ABSTRACT FROM AUTHOR]

This paper presents a buck-boost dc-dc converter for LED drivers capable of delivering an output current ranging from 0.1 to 2 A and a variable output voltage ranging between 2 and 5 V, starting from an input voltage spanning from 2.7 to 5.5 V. The dc-dc converter, realized in a 0.18-μm CMOS technology with 5-V option, occupies an area of 4 mm2 including pads. The circuit features automatic mode switching and dynamic sizing of the power transistors to achieve a peak efficiency of 91%. With a switching frequency of 2.5 MHz, the achieved line regulation is lower than 0.1% V-1 and the output voltage ripple is less than 10 mV. The obtained turn-on and load transient settling time are lower than 40 μs, thus allowing pulsed operation of the LEDs, as well as switching among LEDs of different colors. [ABSTRACT FROM AUTHOR]

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma-delta ( $$\Upsigma\Updelta$$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers. [ABSTRACT FROM AUTHOR]

Abstract: This paper summarizes the results of our research activity in the field of gas-sensing systems, with particular focus on high dynamic-range (DR) integrated interface circuits. This activity was stimulated and strongly encouraged by Prof. Arnaldo D’Amico over the last ten years. The availability of large DR integrated interface circuits is absolutely necessary to turn metal-oxide chemoresistive sensors into effective gas-sensing systems. In this paper we overview different techniques for achieving read-out circuits with DR spanning from 140dB to 160dB and we present the experimental results obtained from three different test chips. The first and the second test chips implement a multi-scale auto-ranging read-out circuit and an oscillator-based read-out circuit, respectively, while the third test chip implements a complete gas-sensing system, including a sensor temperature control circuit as well as an oscillator-based read-out circuit. The results achieved demonstrate that metal-oxide chemoresistive sensors in combination with suitable integrated interface circuits are promising candidates for realizing low-cost portable gas-sensing systems. [Copyright &y& Elsevier]

This paper proposes a 1-A, 6.4-MHz switching frequency DC-DC converter with embedded digital controller, implemented in 65-nm CMOS technology. The proposed DC-DC converter, exploiting a customized, multi-function SAR ADC and a non-linear PID controller, can switch automatically between continuous-conduction mode and pulse-skipping mode, thus maintaining a fairly large efficiency also for light loads. Moreover, a feedforward path in the digital control loop, implemented using the SAR ADC for converting also the battery voltage, significantly improves the line transient performance. The DC-DC converter, which occupies an area of 0.038 mm^2, consumes 115.5 \muA, and requires an external inductance as low as 470 nH, is particularly suited for portable applications. [ABSTRACT FROM PUBLISHER]

This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-μm CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 μW, leading to a Figure of Merit as low as 56 fJ/conversion-level. [ABSTRACT FROM AUTHOR]

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm2. [ABSTRACT FROM AUTHOR]

We present a mixed-signal CMOS front-end cell designed for semiconductor pixel detectors for X-γ ray imaging and spectroscopy. The Readout Pixel Cell (RPC) comprises an analog and a digital section to accomplish all the functionality of a spectroscopic-grade signal readout. The analog section includes a low noise charge preamplifier, a two stage shaper amplifier with digitally selectable shaping times from 1 μs to 10 μs, a baseline restorer, a high precision peak stretcher and an output amplifier. The digital section includes an amplitude discriminator with coarse and fine digital control of the threshold level, a peak discriminator, a current-mode trigger generator, a logic circuit to accomplish the pulse pile-up rejection and the RPC reset after the A/D conversion, the disable functions of the preamplifier and of the discriminators. The RPC has been designed and manufactured in 0.35 μm CMOS technology with a size of 300 μm × 300 μm. The full functionality of the RPC has been successfully tested. At room temperature, the intrinsic equivalent noise charge is 15.7 electrons r.m.s. at 3.3 jis and the minimum noise slope is 22 electrons/pF at 8 μs, the linearity error is between -1.4% and + 1.2% within 1.9 fC input signal dynamic. The RPC has separate voltage supplies (+3.3 V) and grounds for the analog and digital sections and the total power consumption is 495 μW. [ABSTRACT FROM AUTHOR]

A bandpass ΣΔ modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of! MHz with 72 dBFS DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 μm CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 dBc. The power consumption is 16 mW with 1.8 V supply. [ABSTRACT FROM AUTHOR]

An analog baseband chain for a multistandard (Blue- tooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 μm CMOS occupying 1.65 mm² is presented. The circuit consits of an open-loop programmable-gain amplifier (PGA1), an Active-Gm-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 ÷ 68 dB, while the input-referred noise (IRN) is 5 nV/ √Hz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain. [ABSTRACT FROM AUTHOR]

In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and γ-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 μm CMOS technology. The active area is 2.24mm2, and it provides a conversion in 2.5 μs (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91. [ABSTRACT FROM AUTHOR]

This paper presents a complete read-out channel suitable for large arrays of X-ray detectors to be used for spectrometry applications in space. The system is fully integrated except for the X-ray detector. It basically consists of a front-end circuit for processing the detector signal, a Wilkinson A/D converter for the analog-to-digital conversion and the digital logic required to ensure the correct handshaking between all the blocks of the read-out channel. The system allows us to process the signal provided by the detector down to the final analog-to-digital conversion. All these functionalities are embedded in a single chip that, in its final version, will be bump-bonded to the matrix of X-ray detectors. The chip, designed in a 0.35 µm CMOS technology, achieves an input-referred noise of 34 erms-, consuming 0.9 mW from a 3.3 V power supply. The on-board A/D converter features 10 bits of resolution with a maximum conversion time of 210 µs. The INL and DNL of the whole read-out channel are equal to ±3.3 LSB and ±0.2 LSB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we present the design and the characterization of a wide-dynamic-range interface circuit for resistive gas-sensors able to operate without calibration. The circuit is based on resistance-to-frequency conversion, which guarantees low complexity. The state-of-the-art of this measurement method has been improved first by separating the Resistance value Controlled Oscillator circuit (RCO) from the sensing device, thus leading to higher linearity performance, and then by exploiting a novel digital frequency measurement system. Measurement results on a silicon prototype, designed in a 035-µm CMOS technology, show that the circuit achieves, without calibration, a precision in resistance measurement of 0.4% over a range of 4 decades and better than 0.8% over 5 decades (dynamic range, DR = 141 dB). Furthermore, after calibration, it reaches a precision of 0.4% for resistance values ranging between 1 kΩ and 1 GΩ, thus leading to a DR of 168 dB. The prototype chip consumes less than 15 mW from a 3.3-V supply. [ABSTRACT FROM AUTHOR]

In this paper an integrated wide-dynamic-range interface circuit for resistive gas-sensors arrays is presented. The proposed device consists of a multi-scale transresistance continuous time amplifier followed by a 13-bit incremental A/D converter. The circuit selects automatically the scale to use for each measurement and includes two digital-to-analog converters for the calibration of offset and gain of each scale. The proposed interface circuit achieves a measurement accuracy almost always better than 0.1% over a sensor resistance range of more than 5 decades [100 Ω–20 MΩ], leading to an equivalent dynamic range of about 160 dB. The chip has been realized with a 0.35 μm CMOS technology and occupies an area of 3.1 mm2 consuming 6 mW from a 3.3 V power supply. [ABSTRACT FROM AUTHOR]

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-µm CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 109 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm² and 0.7 mm² die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth. [ABSTRACT FROM AUTHOR]

In this paper, we present a switched-capacitor sigma--delta (Σ--Δ) modulator for high resolution applications. In particular, this Σ--Δ modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 μm CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits. [ABSTRACT FROM AUTHOR]

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency. [ABSTRACT FROM AUTHOR]

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal 'CLKSampling' to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (f s)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the 'CLKSampling' signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical f s of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoM WN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum f s with all the sections of the ADC operating at 3.3 V. The FoM WN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we present an Earth magnetic field measurement system and an automated acquisition setup to characterize it. The measurement system consists of a fluxgate sensor and an integrated front-end circuit, both realized in CMOS technology. The couple of orthogonal axes of the sensor makes the system suitable for realizing an electronic compass device. Indeed, we can measure not only the amplitude of the Earth magnetic field (whose full-scale value is of the order of 60μT), but also its direction. The complete measurement system achieves a maximum angular error of 1.5° in the measurement of the Earth magnetic field direction. Furthermore, an acquisition setup was developed to evaluate the measurement system performance. It consists of a precision mechanical plastic structure, in tower form, a microcontroller-based interface circuit, that provides a digital output through an RS232 serial interface, a PC software suitably developed to post-process the data from the acquisition system and a couple of Helmholtz coils to evaluate the linearity of the system. This setup allows us to perform a completely automated and numerically controlled characterization of the measurement system. [Copyright &y& Elsevier]