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In this study, we proposed a pre-distorted driver of a power amplifier in which the driver stage can serve as a pre-distorter of the power stage. In order to secure the linearity of the power amplifier, AM-PM distortions according to the input power of the common-source (CS) and two stacked-FET structures were analyzed and compared with the simulated results. Based on the analyzed AM-PM distortions of the two structure, it was verified that the driver stage with CS structure can act as a pre-distorter of the power stage with the two stacked-FET structure by optimizing the bias voltages of the two structures. The Ka-band power amplifier was designed with a 65-nm CMOS process to verify the feasibility of the proposed pre-distorted driver stage. At 28 GHz, the measured P1dB, saturated output power (P $_{\mathrm {SAT}}$ ), and peak power-added efficiency (PAE) were 18.6 dBm, 19.7 dBm, and 32.9%, respectively. The measured small signal gain was 24.1 dB. When 5G-NR modulation signals (64-QAM, 100-Msym/s, 9.7-dB PAPR) were used, under conditions where the EVM was less than –25 dB, the measured output power and ACLR were 13.3 dBm and –29.4 dBc, respectively.

A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/ $\mu \text{s}$ sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth. [ABSTRACT FROM AUTHOR]

A phase-delay cold-FET pre-distortion linearizer technique is proposed to improve the gain compensation ability compared with the conventional cold-FET pre-distortion linearizer. The gain expansion analysis of the power amplifier (PA) cascading with a pre-distortion linearizer and the comparison with the conventional linearizer and the proposed phase-delay linearizer are provided in this paper. To demonstrate the feasibility of this concept, a single-ended V-band cascode PA with the 90^\circ phase-delay linearizer and a differential K-band common-source PA with the 180^\circ phase-delay linearizer are developed to verify the characteristics. The V-band PA implemented in 90-nm CMOS process exhibits the output 1-dB compression power (OP1~dB) of 13.7 dBm and the power-added efficiency (PAE) at OP1~dB of 14.3%. The K-band PA implemented in 0.18- \mum CMOS process demonstrates 17.5-dBm OP1~dB and 13.6% PAE at OP1~dB. [ABSTRACT FROM AUTHOR]

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1~dB of 7.3 dBm from 1.2 V supply. After linearization, the OP1~dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP1~dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB. [ABSTRACT FROM PUBLISHER]