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A 40–56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross-talk noise injection cases are also presented. [ABSTRACT FROM AUTHOR]

This paper describes a 32.75-Gb/s voltage-mode transmitter (TX) with three-tap feed forward equalization that is fabricated in a 16-nm FinFET CMOS technology. The TX uses a dual regulator architecture to allow independent control of output swing, output common-mode, and equalization. A hybrid impedance control scheme is presented where the total number of driver slices is used for coarse impedance control, and analog loop-based voltage control is used for fine impedance control of the TX. A finite-impulse response compensation circuit to compensate for the data dependent current due to equalization is also presented. The TX consumes 120.8 mW with 0.9- and 1.2-V supplies, provides 0.25–0.9 Vpp output swing, and achieves total jitter of 6.49 ps–pp and random jitter of 220 fs–rms at 32.75 Gb/s with bit error rate of 1e-12. [ABSTRACT FROM AUTHOR]

This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance techniques employed include a fully adaptive continuous-time linear equalizer, automatic gain control, an 11-tap decision feedback equalizer, wideband LC phase-locked loops, and a high-tracking-bandwidth clock and data recovery loop with low latency. Low-power techniques such as half-rate clocking, active inductors and data-rate programmability are employed to meet stringent power budgets at the different rates. At 16.3 Gb/s, the receiver has a jitter tolerance of >0.3UI at 100 MHz. The transceiver achieves a bit error rate < 10e − 15 with up to 28-dB loss at Nyquist. It consumes 219 mW/channel at 16.3 Gb/s. The design has robust performance across process, voltage, and temperature, and the architecture allows for a high degree of tuning to handle different system environments in deployment. [ABSTRACT FROM AUTHOR]

A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid analog and digital equalizations. The analog equalization is performed using two identical stages of continuous time linear equalizer, each having a constant of ~0-dB dc-gain and a maximum peaking of ~7 dB peaking at 14 GHz. A 28-GSample/s 32-way time-interleaved SAR ADC converts the equalized analog signal into digital domain for further equalization using digital signal processing. The transceiver achieves <1e-8 bit error rate over a backplane channel with 31-dB loss at 14-GHz and 3.5-mVrms additional crosstalk, using a fixed ~10-dB TX equalization and an adaptive hybrid RX equalization, with the DSP configured to have a 24-tap feed forward equalizer and a 1-tap decision feedback equalizer. The transceiver consumes 550-mW power at 56 Gb/s, excluding the power of the on-chip configurable DSP that cannot be accurately measured as it is implemented as part of a larger test structure. [ABSTRACT FROM AUTHOR]

This paper describes a 0.5–16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER < 10^-15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes. [ABSTRACT FROM PUBLISHER]